| /gem5/src/cpu/ |
| H A D | quiesce_event.cc | 50 EndQuiesceEvent::description() const argument
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| /gem5/src/arch/arm/insts/ |
| H A D | data64.cc | 46 DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
55 DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
65 DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
74 DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
83 DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
94 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
106 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
118 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
131 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
145 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
160 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
173 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
188 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument
[all...] |
| H A D | branch.cc | 47 BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
56 BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
65 BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| H A D | sve_mem.cc | 78 SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
97 SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
46 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
62 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| H A D | pred_inst.cc | 48 PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
65 PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
79 DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
88 DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
97 DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
106 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
[all...] |
| /gem5/src/arch/sparc/insts/ |
| H A D | micro.cc | 37 SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
|
| H A D | priv.cc | 40 Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
50 RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
63 WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
83 WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| H A D | trap.cc | 38 Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| /gem5/src/arch/riscv/insts/ |
| H A D | mem.cc | 48 Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
57 Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| H A D | compressed.cc | 44 CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | exit_gen.cc | 63 ExitGen::nextPacketTick(bool elastic, Tick delay) const argument
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| H A D | idle_gen.cc | 61 IdleGen::nextPacketTick(bool elastic, Tick delay) const argument
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| /gem5/src/systemc/core/ |
| H A D | sc_interface.cc | 41 sc_interface::default_event() const argument
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| /gem5/src/cpu/o3/probe/ |
| H A D | simple_trace.hh | 66 const std::string name() const { return ProbeListenerObject::name() + ".trace"; } argument
|
| /gem5/src/mem/cache/replacement_policies/ |
| H A D | bip_rp.cc | 44 BIPRP::reset(const std::shared_ptr<ReplacementData>& replacement_data) const argument
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| /gem5/src/base/ |
| H A D | match.hh | 53 bool match(const std::string &name) const argument
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| /gem5/src/mem/ |
| H A D | secure_port_proxy.cc | 43 SecurePortProxy::tryReadBlob(Addr addr, void *p, int size) const argument
50 SecurePortProxy::tryWriteBlob(Addr addr, const void *p, int size) const argument
57 SecurePortProxy::tryMemsetBlob(Addr addr, uint8_t v, int size) const argument
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| /gem5/src/dev/ |
| H A D | baddev.hh | 58 params() const argument
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractEntry.cc | 41 AbstractEntry::getPermission() const argument
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| /gem5/src/mem/ruby/system/ |
| H A D | RubyPortProxy.hh | 94 int outstandingCount() const { return 0; } argument
103 bool isDeadlockEventScheduled() const { return false; } argument
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| /gem5/ext/dsent/libutil/ |
| H A D | Exception.cc | 33 const char* Exception::what() const throw() argument
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| /gem5/src/arch/power/insts/ |
| H A D | condition.cc | 36 CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
49 CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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| /gem5/src/dev/i2c/ |
| H A D | device.hh | 92 uint8_t i2cAddr() const { return _addr; } argument
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| /gem5/src/gpu-compute/ |
| H A D | hsa_object.hh | 65 const st argument
[all...] |
| /gem5/src/dev/mips/ |
| H A D | malta_cchip.hh | 85 params() const argument
|