15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Rick Strong 305222Sksewell@umich.edu */ 315222Sksewell@umich.edu 325222Sksewell@umich.edu/** @file 335222Sksewell@umich.edu * Emulation of the Malta CChip CSRs 345222Sksewell@umich.edu */ 355222Sksewell@umich.edu 365222Sksewell@umich.edu#ifndef __MALTA_CCHIP_HH__ 375222Sksewell@umich.edu#define __MALTA_CCHIP_HH__ 385222Sksewell@umich.edu 395222Sksewell@umich.edu#include "dev/mips/malta.hh" 405222Sksewell@umich.edu#include "dev/io_device.hh" 415222Sksewell@umich.edu#include "params/MaltaCChip.hh" 425222Sksewell@umich.edu 435222Sksewell@umich.edu/** 445222Sksewell@umich.edu * Malta CChip CSR Emulation. This device includes all the interrupt 455222Sksewell@umich.edu * handling code for the chipset. 465222Sksewell@umich.edu */ 475222Sksewell@umich.educlass MaltaCChip : public BasicPioDevice 485222Sksewell@umich.edu{ 495222Sksewell@umich.edu protected: 505222Sksewell@umich.edu /** 515222Sksewell@umich.edu * pointer to the malta object. 525222Sksewell@umich.edu * This is our access to all the other malta 535222Sksewell@umich.edu * devices. 545222Sksewell@umich.edu */ 555222Sksewell@umich.edu Malta *malta; 565222Sksewell@umich.edu 575222Sksewell@umich.edu /** 585222Sksewell@umich.edu * The dims are device interrupt mask registers. 595222Sksewell@umich.edu * One exists for each CPU, the DRIR X DIM = DIR 605222Sksewell@umich.edu */ 615222Sksewell@umich.edu //uint64_t dim[Malta::Max_CPUs]; 625222Sksewell@umich.edu 635222Sksewell@umich.edu /** 645222Sksewell@umich.edu * The dirs are device interrupt registers. 655222Sksewell@umich.edu * One exists for each CPU, the DRIR X DIM = DIR 665222Sksewell@umich.edu */ 675222Sksewell@umich.edu //uint64_t dir[Malta::Max_CPUs]; 685222Sksewell@umich.edu 695222Sksewell@umich.edu /** 705222Sksewell@umich.edu * This register contains bits for each PCI interrupt 715222Sksewell@umich.edu * that can occur. 725222Sksewell@umich.edu */ 735222Sksewell@umich.edu //uint64_t drir; 745222Sksewell@umich.edu 755222Sksewell@umich.edu /** Indicator of which CPUs have an IPI interrupt */ 765222Sksewell@umich.edu //uint64_t ipint; 775222Sksewell@umich.edu 785222Sksewell@umich.edu /** Indicator of which CPUs have an RTC interrupt */ 795222Sksewell@umich.edu //uint64_t itint; 805222Sksewell@umich.edu 815222Sksewell@umich.edu public: 825222Sksewell@umich.edu typedef MaltaCChipParams Params; 835222Sksewell@umich.edu 845222Sksewell@umich.edu const Params * 855222Sksewell@umich.edu params() const 865222Sksewell@umich.edu { 875222Sksewell@umich.edu return dynamic_cast<const Params *>(_params); 885222Sksewell@umich.edu } 895222Sksewell@umich.edu 905222Sksewell@umich.edu /** 915222Sksewell@umich.edu * Initialize the Malta CChip by setting all of the 925222Sksewell@umich.edu * device register to 0. 935222Sksewell@umich.edu * @param p params struct 945222Sksewell@umich.edu */ 955222Sksewell@umich.edu MaltaCChip(Params *p); 965222Sksewell@umich.edu 9711347Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 985222Sksewell@umich.edu 9911347Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 1005222Sksewell@umich.edu 1015222Sksewell@umich.edu /** 1025222Sksewell@umich.edu * post an RTC interrupt to the CPU 1035222Sksewell@umich.edu */ 1045222Sksewell@umich.edu void postRTC(); 1055222Sksewell@umich.edu 1065222Sksewell@umich.edu /** 1075222Sksewell@umich.edu * post an interrupt to the CPU. 1085222Sksewell@umich.edu * @param interrupt the interrupt number to post (0-7) 1095222Sksewell@umich.edu */ 1105222Sksewell@umich.edu void postIntr(uint32_t interrupt); 1115222Sksewell@umich.edu 1125222Sksewell@umich.edu /** 1135222Sksewell@umich.edu * clear an interrupt previously posted to the CPU. 1145222Sksewell@umich.edu * @param interrupt the interrupt number to post (0-7) 1155222Sksewell@umich.edu */ 1165222Sksewell@umich.edu void clearIntr(uint32_t interrupt); 1175222Sksewell@umich.edu 1185222Sksewell@umich.edu /** 1195222Sksewell@umich.edu * post an ipi interrupt to the CPU. 1205222Sksewell@umich.edu * @param ipintr the cpu number to clear(bitvector) 1215222Sksewell@umich.edu */ 1225222Sksewell@umich.edu void clearIPI(uint64_t ipintr); 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu /** 1255222Sksewell@umich.edu * clear a timer interrupt previously posted to the CPU. 1265222Sksewell@umich.edu * @param itintr the cpu number to clear(bitvector) 1275222Sksewell@umich.edu */ 1285222Sksewell@umich.edu void clearITI(uint64_t itintr); 1295222Sksewell@umich.edu 1305222Sksewell@umich.edu /** 1315222Sksewell@umich.edu * request an interrupt be posted to the CPU. 1325222Sksewell@umich.edu * @param ipreq the cpu number to interrupt(bitvector) 1335222Sksewell@umich.edu */ 1345222Sksewell@umich.edu void reqIPI(uint64_t ipreq); 1355222Sksewell@umich.edu 13611168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 13711168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1385222Sksewell@umich.edu}; 1395222Sksewell@umich.edu 1405222Sksewell@umich.edu#endif // __MALTA_CCHIP_HH__ 141