| /gem5/src/mem/ruby/system/ |
| H A D | WeightedLRUReplacementPolicy.py | 42 cache = Param.RubyCache("") variable in class:WeightedLRUReplacementPolicy
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| /gem5/src/mem/cache/ |
| H A D | write_queue_entry.cc | 142 WriteQueueEntry::sendPacket(BaseCache &cache) argument
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| H A D | mshr.cc | 653 sendPacket(BaseCache &cache) argument
[all...] |
| H A D | base.hh | 168 BaseCache &cache; member in class:BaseCache::CacheReqPacketQueue
173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port, SnoopRespPacketQueue &snoop_resp_queue, const std::string &label) argument
222 BaseCache *cache; member in class:BaseCache::MemSidePort
290 BaseCache *cache; member in class:BaseCache::CpuSidePort
[all...] |
| /gem5/ext/dsent/model/std_cells/ |
| H A D | BUF.cc | 87 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
113 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
158 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | INV.cc | 95 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
121 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
176 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | AND2.cc | 100 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
128 Map<double>* cache local
210 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | LATQ.cc | 103 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
131 Map<double>* cache local
230 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | NAND2.cc | 102 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
125 Map<double>* cache local
206 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | NOR2.cc | 102 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
125 Map<double>* cache local
205 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | OR2.cc | 95 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
123 Map<double>* cache local
201 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | XOR2.cc | 99 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
129 Map<double>* cache local
220 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | DFFQ.cc | 109 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
137 Map<double>* cache local
275 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | MUX2.cc | 106 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
138 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
239 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| H A D | ADDF.cc | 126 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
162 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local
334 Map<double>* cache = cell_lib_->getStdCellCache(); local
[all...] |
| /gem5/src/mem/cache/prefetch/ |
| H A D | base.hh | 261 BaseCache* cache; member in class:BasePrefetcher
[all...] |
| /gem5/ext/mcpat/cacti/ |
| H A D | io.cc | 671 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int banks, double tech_node, int page_sz, int burst_length, int pre_width, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int is_nuca, int core_count, int cache_level, int nuca_bank_count, int nuca_obj_func_delay, int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, int nuca_obj_func_area, int nuca_obj_func_cycle_time, int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, int nuca_dev_func_leakage_power, int nuca_dev_func_area, int nuca_dev_func_cycle_time, int REPEATERS_IN_HTREE_SEGMENTS_in, int p_input) argument
861 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int search_ports, int banks, double tech_node, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_cycle_time, int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, int ndsam1, int ndsam2, int ecc) argument
[all...] |
| /gem5/ext/pybind11/include/pybind11/ |
| H A D | pybind11.h | 2033 auto &cache = detail::get_internals().inactive_overload_cache; local
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| H A D | pytypes.h | 520 mutable object cache; member in class:accessor
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