mem/cache/base.hh

49  * Declares a basic cache interface BaseCache.
66 #include "mem/cache/cache_blk.hh"
67 #include "mem/cache/compressors/base.hh"
68 #include "mem/cache/mshr_queue.hh"
69 #include "mem/cache/tags/base.hh"
70 #include "mem/cache/write_queue.hh"
71 #include "mem/cache/write_queue_entry.hh"
91  * A basic cache interface. Implements some common functions for speed.
118      * A cache master port is used for the memory-side port of the
119      * cache, and in addition to the basic timing port that only sends
159      * the memory-side cache port to also send requests based on the
161      * cache implementation and is used by the MemSidePort.
168         BaseCache &cache;
173         CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
176             ReqPacketQueue(cache, port, label), cache(cache),
196             if (snoopRespQueue.checkConflict(pkt, cache.blkSize)) {
209      * The memory-side port extends the base cache master port with
216         /** The cache-specific queue. */
221         // a pointer to our specific cache implementation
222         BaseCache *cache;
241      * A cache slave port is used for the CPU-side port of the cache,
282      * The CPU-side port extends the base cache slave port with access
289         // a pointer to our specific cache implementation
290         BaseCache *cache;
332     /** To probe when a cache hit occurs */
335     /** To probe when a cache miss occurs */
338     /** To probe when a cache fill occurs */
349      * any whole-line writes. Normally the cache allocates the line
358      * Temporary cache block for occasional transitory use.  We use
397      * cache is mostly inclusive with regards to the upstream cache(s)
399      * requests). In the case of a mostly exclusive cache, we allocate
400      * on fill if the packet did not come from a cache, thus if we:
442      * @param blk The cache block that was accessed.
453      * @param blk The cache block to be updated.
462      * Handle a timing request that hit in the cache
472      * Handle a timing request that missed in the cache
474      * Implementation specific handling for different cache
487      * Handle a timing request that missed in the cache
489      * Common functionality across different cache implementations
493      * @param mshr Any existing mshr for the referenced cache block
526      * Handles a response (cache line fill/write ack) from the bus.
544      * Handle a request in atomic mode that missed in this cache
566      * Snoop for the provided request in the cache and return the estimated
625      * cases where a downstream cache is mostly inclusive we likely
626      * want it to act as a victim cache also for lines that have not
702      * Maintain the clusivity of this cache by potentially
707      * @param from_cache Whether we have dealt with a packet from a cache
715      * Populates a cache block and handles all outstanding requests for the
725      * @param blk The cache block if it already exists.
728      * @return Pointer to the new cache block.
747      * Evict a cache block.
757      * Evict a cache block.
767      * Invalidate a cache block.
784      * Creates a request that writes the block to the cache below
785      * without evicting the block from the current cache.
795      * Write back dirty blocks in the cache using functional accesses.
800      * Invalidates all blocks in the cache.
802      * @warn Dirty cache lines will not be written back to
809      * Determine if there are any dirty blocks in the cache.
817      * cache. This is useful to filter snoops.
830     /** Block size of this cache */
834      * The latency of tag lookup of a cache. It occurs when there is
835      * an access to the cache.
840      * The latency of data access of a cache. It occurs when there is
841      * an access to the cache.
846      * This is the forward latency of the cache. It occurs when there
847      * is a cache miss and a request is forwarded downstream, in
852     /** The latency to fill a cache block */
856      * The latency of sending reponse to its upper level cache/core on
874      * Clusivity with respect to the upstream cache, determining if we
875      * fill into both this cache and the cache above on a miss. Note
881      * Is this cache read only, for example the instruction cache, or
882      * table-walker cache. A cache that is read only should never see
897     /** Stores time the cache blocked for statistics. */
907      * The address range to which the cache responds on the CPU side.
970     /** The number of times this cache blocked for each blocked cause. */
1060      * Query block size of a cache.
1122      * Returns true if the cache is blocked for accesses.
1130      * Marks the access path of the cache as blocked for the given cause. This
1132      * @param cause The reason for the cache blocking.
1147      * Marks the cache as unblocked for the given cause. This also clears the
1151      * access the cache. The cache must be in a state to handle that request.
1202                 exitSimLoop("A cache reached the maximum miss count");
1213      * Checks if the cache is coalescing writes
1215      * @return True if the cache is coalescing writes
1221      * Cache block visitor that writes back dirty cache blocks using
1227      * Cache block visitor that invalidates all blocks in the cache.
1229      * @warn Dirty cache lines will not be written back to memory.
1256      * We currently don't support checkpointing cache state, so this panics.
1275  * the cache but rather send a whole line write to the memory below.
1292      * @return return true if the cache should coalesce writes.
1301      * @return return true if the cache should not allocate for writes.
1337      * @param blk_addr The accessed cache block