History log of /gem5/src/arch/arm/isa/insts/macromem.isa
Revision Date Author Comments
# 13544:0b4e5446167c 13-Oct-2018 Gabe Black <gabeblack@google.com>

arm: Stop using the FloatReg and FloatRegBits types.

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>


# 12134:604f47f63877 24-May-2017 Gedare Bloom <gedare@rtems.org>

arch-arm: fix ldm of pc interswitching branch

The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
The interswitch is broken prior to this commit, with LDM to the PC
ignoring the switch.

Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Reviewed-on: https://gem5-review.googlesource.com/3520
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>


# 11355:46c7b3e35720 29-Feb-2016 Mitch Hayenga <mitch.hayenga@arm.com>

arm: Squash after returning from exceptions in v7

Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.


# 10474:799c8ee4ecba 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".


# 10346:d96b61d843b2 03-Sep-2014 Mitch Hayenga <mitch.hayenga@arm.com>

arm: Make memory ops work on 64bit/128-bit quantities

Multiple instructions assume only 32-bit load operations are available,
this patch increases load sizes to 64-bit or 128-bit for many load pair and
load multiple instructions.


# 10037:5cac77888310 24-Jan-2014 ARM gem5 Developers

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black


# 8607:5fb918115c07 31-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.


# 8588:ef28ed90449d 27-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.


# 8309:d1ce92fd3245 18-May-2011 Nathan Binkert <nate@binkert.org>

gcc: fix an uninitialized variable warning from G++ 4.5


# 8304:16911ff780d3 13-May-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Construct the predicate test register for more instruction programatically.

If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.


# 8303:5a95f1d2494e 13-May-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.


# 8302:9f23d01421de 13-May-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.


# 8301:858384f3af1c 13-May-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.


# 8285:c38905a6fa32 04-May-2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com>

ARM: Implement WFE/WFI/SEV semantics.


# 8205:7ecbffb674aa 04-Apr-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Cleanup implementation of ITSTATE and put important code in PCState.

Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.


# 8148:93982cb5044c 17-Mar-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Fix subtle bug in LDM.

If the instruction faults mid-op the base register shouldn't be written back.


# 8140:7449084b1612 17-Mar-2011 Matt Horsnell <Matt.Horsnell@arm.com>

ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.


# 8139:2b2efc67f6df 17-Mar-2011 Matt Horsnell <Matt.Horsnell@arm.com>

ARM: Rename registers used as temporary state by microops.


# 7858:ee6641d7c713 18-Jan-2011 Matt.Horsnell <Matt.Horsnell@arm.com>

O3: Fix itstate prediction and recovery.

Any change of control flow now resets the itstate to 0 mask and 0 condition,
except where the control flow alteration write into the cpsr register. These
case, for example return from an iterrupt, require the predecoder to recover
the itstate.

As there is a window of opportunity between the return from an interrupt
changing the control flow at the head of the pipe and the commit of the update
to the CPSR, the predecoder needs to be able to grab the ITstate early. This
is now handled by setting the forcedItState inside a PCstate for the control
flow altering instruction.

That instruction will have the correct mask/cond, but will not have a valid
itstate until advancePC is called (note this happens to advance the execution).
When the new PCstate is copy constructed it gets the itstate cond/mask, and
upon advancing the PC the itstate becomes valid.

Subsequent advancing invalidates the state and zeroes the cond/mask. This is
handled in isolation for the ARM ISA and should have no impact on other ISAs.

Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.


# 7797:998b217dcae7 09-Dec-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Take advantage of new PCState syntax.


# 7720:65d338a8dba4 31-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.


# 7648:3e561a5c0456 25-Aug-2010 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing


# 7646:a444dbee8c07 25-Aug-2010 Gene WU <gene.wu@arm.com>

ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.


# 7644:62873d5c2bfc 25-Aug-2010 Ali Saidi <ali.saidi@arm.com>

ARM: Fix VFP enabled checks for mem instructions


# 7639:8c09b7ff5b57 25-Aug-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Implement all ARM SIMD instructions.


# 7422:feddb9077def 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Decode to specialized conditional/unconditional versions of instructions.

This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.


# 7408:ee6949c5bb5b 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.


# 7400:f6c9b27c4dbe 02-Jun-2010 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Implement ARM CPU interrupts


# 7342:72166bc39ff8 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Fix the implementation of the VFP ldm and stm macroops.

There were four bugs in these instructions. First, the loaded value was being
stored into a floating point register as floating point, changing the value as
it was transfered. Second, the meaning of the "up" bit had been reversed.
Third, the statically sized microop array wasn't bit enough for all possible
inputs. It's now dynamically sized and should always be big enough. Fourth,
the offset was stored as an unsigned 8 bit value. Negative offsets would look
like moderately large positive offsets.


# 7303:6b70985664c8 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Implement the strex instructions.


# 7296:27c60324ec4d 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Respect the E bit of the CPSR when doing loads and stores.


# 7207:82cfe1198d6f 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Make LDM that loads the PC perform an interworking branch.


# 7187:53d0ec9111bc 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Make ldrs into the PC and ldm exception return do interworking branches.


# 7179:f9151566ca6e 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Define the VFP load/store multiple instructions.


# 7174:b8fe16a5e349 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Add floating point load/store microops.


# 7170:6f97f5107abe 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Move the macro mem constructor out of the isa desc.
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.


# 7169:6cc400372260 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Make macroops panic if executed directly.
The macroop should never be executed, only it's microops will.


# 7134:60fe8a00b36e 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Reimplement load/store multiple external to the decoder.