macromem.isa revision 7400:f6c9b27c4dbe 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42//          Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49let {{
50    predicateTest = 'testPredicate(CondCodes, condCode)'
51}};
52
53let {{
54    microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
55    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
56                                   'MicroMemOp',
57                                   {'memacc_code': microLdrUopCode,
58                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
59                                    'predicate_test': predicateTest},
60                                   ['IsMicroop'])
61
62    microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
63    microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
64                                     'MicroMemOp',
65                                     {'memacc_code': microLdrFpUopCode,
66                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
67                                      'predicate_test': predicateTest},
68                                     ['IsMicroop'])
69
70    microLdrRetUopCode = '''
71        CPSR cpsr = Cpsr;
72        SCTLR sctlr = Sctlr;
73        uint32_t newCpsr =
74            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
75        Cpsr = ~CondCodesMask & newCpsr;
76        CondCodes = CondCodesMask & newCpsr;
77        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
78    '''
79    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
80                                      'MicroMemOp',
81                                      {'memacc_code': microLdrRetUopCode,
82                                       'ea_code':
83                                          'EA = Rb + (up ? imm : -imm);',
84                                       'predicate_test': predicateTest},
85                                      ['IsMicroop'])
86
87    microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
88    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
89                                   'MicroMemOp',
90                                   {'memacc_code': microStrUopCode,
91                                    'postacc_code': "",
92                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
93                                    'predicate_test': predicateTest},
94                                   ['IsMicroop'])
95
96    microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
97    microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
98                                     'MicroMemOp',
99                                     {'memacc_code': microStrFpUopCode,
100                                      'postacc_code': "",
101                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
102                                      'predicate_test': predicateTest},
103                                     ['IsMicroop'])
104
105    header_output = decoder_output = exec_output = ''
106
107    loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop)
108    storeIops = (microStrUopIop, microStrFpUopIop)
109    for iop in loadIops + storeIops:
110        header_output += MicroMemDeclare.subst(iop)
111        decoder_output += MicroMemConstructor.subst(iop)
112    for iop in loadIops:
113        exec_output += LoadExecute.subst(iop) + \
114                       LoadInitiateAcc.subst(iop) + \
115                       LoadCompleteAcc.subst(iop)
116    for iop in storeIops:
117        exec_output += StoreExecute.subst(iop) + \
118                       StoreInitiateAcc.subst(iop) + \
119                       StoreCompleteAcc.subst(iop)
120}};
121
122////////////////////////////////////////////////////////////////////
123//
124// Integer = Integer op Immediate microops
125//
126
127let {{
128    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
129                                    'MicroIntOp',
130                                    {'code': 'Ra = Rb + imm;',
131                                     'predicate_test': predicateTest},
132                                    ['IsMicroop'])
133
134    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
135                                    'MicroIntOp',
136                                    {'code': 'Ra = Rb - imm;',
137                                     'predicate_test': predicateTest},
138                                    ['IsMicroop'])
139
140    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
141                    MicroIntDeclare.subst(microSubiUopIop)
142    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
143                     MicroIntConstructor.subst(microSubiUopIop)
144    exec_output = PredOpExecute.subst(microAddiUopIop) + \
145                  PredOpExecute.subst(microSubiUopIop)
146}};
147
148let {{
149    iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
150    header_output = MacroMemDeclare.subst(iop)
151    decoder_output = MacroMemConstructor.subst(iop)
152
153    vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
154    header_output += MacroVFPMemDeclare.subst(vfpIop)
155    decoder_output += MacroVFPMemConstructor.subst(vfpIop)
156}};
157