macromem.isa revision 7134:60fe8a00b36e 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42//          Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49let {{
50    predicateTest = 'testPredicate(CondCodes, condCode)'
51}};
52
53let {{
54    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
55                                   'MicroMemOp',
56                                   {'memacc_code': 'Ra = Mem;',
57                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
58                                    'predicate_test': predicateTest},
59                                   ['IsMicroop'])
60
61    microLdrRetUopCode = '''
62        Ra = Mem;
63        uint32_t newCpsr =
64            cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
65        Cpsr = ~CondCodesMask & newCpsr;
66        CondCodes = CondCodesMask & newCpsr;
67    '''
68    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
69                                      'MicroMemOp',
70                                      {'memacc_code': microLdrRetUopCode,
71                                       'ea_code':
72                                          'EA = Rb + (up ? imm : -imm);',
73                                       'predicate_test': predicateTest},
74                                      ['IsMicroop'])
75
76    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
77                                   'MicroMemOp',
78                                   {'memacc_code': 'Mem = Ra;',
79                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
80                                    'predicate_test': predicateTest},
81                                   ['IsMicroop'])
82
83    header_output = MicroMemDeclare.subst(microLdrUopIop) + \
84                    MicroMemDeclare.subst(microLdrRetUopIop) + \
85                    MicroMemDeclare.subst(microStrUopIop)
86    decoder_output = MicroMemConstructor.subst(microLdrUopIop) + \
87                     MicroMemConstructor.subst(microLdrRetUopIop) + \
88                     MicroMemConstructor.subst(microStrUopIop)
89    exec_output = LoadExecute.subst(microLdrUopIop) + \
90                  LoadExecute.subst(microLdrRetUopIop) + \
91                  StoreExecute.subst(microStrUopIop) + \
92                  LoadInitiateAcc.subst(microLdrUopIop) + \
93                  LoadInitiateAcc.subst(microLdrRetUopIop) + \
94                  StoreInitiateAcc.subst(microStrUopIop) + \
95                  LoadCompleteAcc.subst(microLdrUopIop) + \
96                  LoadCompleteAcc.subst(microLdrRetUopIop) + \
97                  StoreCompleteAcc.subst(microStrUopIop)
98}};
99
100////////////////////////////////////////////////////////////////////
101//
102// Integer = Integer op Immediate microops
103//
104
105let {{
106    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
107                                    'MicroIntOp',
108                                    {'code': 'Ra = Rb + imm;',
109                                     'predicate_test': predicateTest},
110                                    ['IsMicroop'])
111
112    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
113                                    'MicroIntOp',
114                                    {'code': 'Ra = Rb - imm;',
115                                     'predicate_test': predicateTest},
116                                    ['IsMicroop'])
117
118    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
119                    MicroIntDeclare.subst(microSubiUopIop)
120    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
121                     MicroIntConstructor.subst(microSubiUopIop)
122    exec_output = PredOpExecute.subst(microAddiUopIop) + \
123                  PredOpExecute.subst(microSubiUopIop)
124}};
125
126let {{
127    iop = InstObjParams("ldmstm", "LdmStm", 'PredMacroOp', "", [])
128    header_output = MacroMemDeclare.subst(iop)
129    decoder_output = MacroMemConstructor.subst(iop)
130    exec_output = MacroMemExecute.subst(iop)
131}};
132