macromem.isa revision 8205:7ecbffb674aa
13569Sgblack@eecs.umich.edu// -*- mode:c++ -*- 23569Sgblack@eecs.umich.edu 33569Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 43569Sgblack@eecs.umich.edu// All rights reserved 53569Sgblack@eecs.umich.edu// 63569Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 73569Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 83569Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 93569Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 103569Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 113569Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 123569Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 133569Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 143569Sgblack@eecs.umich.edu// 153569Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 163569Sgblack@eecs.umich.edu// All rights reserved. 173569Sgblack@eecs.umich.edu// 183569Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 193569Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 203569Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 213569Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 223569Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 233569Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 243569Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 253569Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 263569Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 273569Sgblack@eecs.umich.edu// this software without specific prior written permission. 283804Ssaidi@eecs.umich.edu// 293569Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303569Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313918Ssaidi@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323918Ssaidi@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333804Ssaidi@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343811Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353569Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363824Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373811Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383811Ssaidi@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393823Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403823Ssaidi@eecs.umich.edu// 413823Ssaidi@eecs.umich.edu// Authors: Stephen Hines 423569Sgblack@eecs.umich.edu// Gabe Black 434103Ssaidi@eecs.umich.edu 443569Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 453804Ssaidi@eecs.umich.edu// 463804Ssaidi@eecs.umich.edu// Load/store microops 474088Sbinkertn@umich.edu// 483569Sgblack@eecs.umich.edu 493804Ssaidi@eecs.umich.edulet {{ 503881Ssaidi@eecs.umich.edu microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 513881Ssaidi@eecs.umich.edu microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 523804Ssaidi@eecs.umich.edu 'MicroMemOp', 533804Ssaidi@eecs.umich.edu {'memacc_code': microLdrUopCode, 543804Ssaidi@eecs.umich.edu 'ea_code': 'EA = URb + (up ? imm : -imm);', 553804Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 563569Sgblack@eecs.umich.edu ['IsMicroop']) 573804Ssaidi@eecs.umich.edu 583918Ssaidi@eecs.umich.edu microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 593881Ssaidi@eecs.umich.edu microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 603881Ssaidi@eecs.umich.edu 'MicroMemOp', 613881Ssaidi@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 623804Ssaidi@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + 633569Sgblack@eecs.umich.edu 'EA = URb + (up ? imm : -imm);', 643804Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 653804Ssaidi@eecs.umich.edu ['IsMicroop']) 663804Ssaidi@eecs.umich.edu 673804Ssaidi@eecs.umich.edu microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 683881Ssaidi@eecs.umich.edu microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', 693804Ssaidi@eecs.umich.edu 'MicroMemOp', 703804Ssaidi@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 713804Ssaidi@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + ''' 723804Ssaidi@eecs.umich.edu EA = URb + (up ? imm : -imm) + 733804Ssaidi@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 743804Ssaidi@eecs.umich.edu ''', 753804Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 763569Sgblack@eecs.umich.edu ['IsMicroop']) 773569Sgblack@eecs.umich.edu 783804Ssaidi@eecs.umich.edu microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 793804Ssaidi@eecs.umich.edu microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', 803826Ssaidi@eecs.umich.edu 'MicroMemOp', 813804Ssaidi@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 823569Sgblack@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + ''' 833569Sgblack@eecs.umich.edu EA = URb + (up ? imm : -imm) - 843804Ssaidi@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 853826Ssaidi@eecs.umich.edu ''', 863907Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 873826Ssaidi@eecs.umich.edu ['IsMicroop']) 883811Ssaidi@eecs.umich.edu 893836Ssaidi@eecs.umich.edu microRetUopCode = ''' 903915Ssaidi@eecs.umich.edu CPSR cpsr = Cpsr; 913907Ssaidi@eecs.umich.edu SCTLR sctlr = Sctlr; 923881Ssaidi@eecs.umich.edu uint32_t newCpsr = 933881Ssaidi@eecs.umich.edu cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 943881Ssaidi@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 953881Ssaidi@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 963907Ssaidi@eecs.umich.edu IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 973881Ssaidi@eecs.umich.edu NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) 983881Ssaidi@eecs.umich.edu | (((CPSR)Spsr).it1 & 0x3); 993881Ssaidi@eecs.umich.edu ''' 1003881Ssaidi@eecs.umich.edu 1013881Ssaidi@eecs.umich.edu microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 1023907Ssaidi@eecs.umich.edu 'MicroMemOp', 1033907Ssaidi@eecs.umich.edu {'memacc_code': 1043907Ssaidi@eecs.umich.edu microRetUopCode % 'Mem.uw', 1053907Ssaidi@eecs.umich.edu 'ea_code': 1063907Ssaidi@eecs.umich.edu 'EA = URb + (up ? imm : -imm);', 1073907Ssaidi@eecs.umich.edu 'predicate_test': condPredicateTest}, 1083907Ssaidi@eecs.umich.edu ['IsMicroop','IsNonSpeculative', 1093907Ssaidi@eecs.umich.edu 'IsSerializeAfter']) 1103907Ssaidi@eecs.umich.edu 1113907Ssaidi@eecs.umich.edu microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);" 1123907Ssaidi@eecs.umich.edu microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 1133907Ssaidi@eecs.umich.edu 'MicroMemOp', 1143907Ssaidi@eecs.umich.edu {'memacc_code': microStrUopCode, 1153907Ssaidi@eecs.umich.edu 'postacc_code': "", 1163907Ssaidi@eecs.umich.edu 'ea_code': 'EA = URb + (up ? imm : -imm);', 1173907Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 1183907Ssaidi@eecs.umich.edu ['IsMicroop']) 1193907Ssaidi@eecs.umich.edu 1203907Ssaidi@eecs.umich.edu microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1213907Ssaidi@eecs.umich.edu microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 1223907Ssaidi@eecs.umich.edu 'MicroMemOp', 1233907Ssaidi@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1243907Ssaidi@eecs.umich.edu 'postacc_code': "", 1253881Ssaidi@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + 1263881Ssaidi@eecs.umich.edu 'EA = URb + (up ? imm : -imm);', 1273881Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 1283881Ssaidi@eecs.umich.edu ['IsMicroop']) 1293881Ssaidi@eecs.umich.edu 1303881Ssaidi@eecs.umich.edu microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1313881Ssaidi@eecs.umich.edu microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop', 1323881Ssaidi@eecs.umich.edu 'MicroMemOp', 1333881Ssaidi@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1343881Ssaidi@eecs.umich.edu 'postacc_code': "", 1353881Ssaidi@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + ''' 1363881Ssaidi@eecs.umich.edu EA = URb + (up ? imm : -imm) + 1373907Ssaidi@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1383811Ssaidi@eecs.umich.edu ''', 1393826Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 1403826Ssaidi@eecs.umich.edu ['IsMicroop']) 1413826Ssaidi@eecs.umich.edu 1423826Ssaidi@eecs.umich.edu microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1433881Ssaidi@eecs.umich.edu microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop', 1443881Ssaidi@eecs.umich.edu 'MicroMemOp', 1453881Ssaidi@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1463881Ssaidi@eecs.umich.edu 'postacc_code': "", 1473881Ssaidi@eecs.umich.edu 'ea_code': vfpEnabledCheckCode + ''' 1483881Ssaidi@eecs.umich.edu EA = URb + (up ? imm : -imm) - 1493881Ssaidi@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1503881Ssaidi@eecs.umich.edu ''', 1513881Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 1523881Ssaidi@eecs.umich.edu ['IsMicroop']) 1533881Ssaidi@eecs.umich.edu 1543881Ssaidi@eecs.umich.edu header_output = decoder_output = exec_output = '' 1553881Ssaidi@eecs.umich.edu 1563881Ssaidi@eecs.umich.edu loadIops = (microLdrUopIop, microLdrRetUopIop, 1573881Ssaidi@eecs.umich.edu microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop) 1583826Ssaidi@eecs.umich.edu storeIops = (microStrUopIop, microStrFpUopIop, 1593826Ssaidi@eecs.umich.edu microStrDBFpUopIop, microStrDTFpUopIop) 1603826Ssaidi@eecs.umich.edu for iop in loadIops + storeIops: 1613826Ssaidi@eecs.umich.edu header_output += MicroMemDeclare.subst(iop) 1623826Ssaidi@eecs.umich.edu decoder_output += MicroMemConstructor.subst(iop) 1633881Ssaidi@eecs.umich.edu for iop in loadIops: 1643569Sgblack@eecs.umich.edu exec_output += LoadExecute.subst(iop) + \ 1653569Sgblack@eecs.umich.edu LoadInitiateAcc.subst(iop) + \ 1663881Ssaidi@eecs.umich.edu LoadCompleteAcc.subst(iop) 1673804Ssaidi@eecs.umich.edu for iop in storeIops: 1683881Ssaidi@eecs.umich.edu exec_output += StoreExecute.subst(iop) + \ 1693826Ssaidi@eecs.umich.edu StoreInitiateAcc.subst(iop) + \ 1703881Ssaidi@eecs.umich.edu StoreCompleteAcc.subst(iop) 1713881Ssaidi@eecs.umich.edu}}; 1723881Ssaidi@eecs.umich.edu 1733907Ssaidi@eecs.umich.edulet {{ 1743907Ssaidi@eecs.umich.edu exec_output = header_output = '' 1753929Ssaidi@eecs.umich.edu 1763929Ssaidi@eecs.umich.edu eaCode = 'EA = URa + imm;' 1773907Ssaidi@eecs.umich.edu 1783907Ssaidi@eecs.umich.edu for size in (1, 2, 3, 4, 6, 8, 12, 16): 1793804Ssaidi@eecs.umich.edu # Set up the memory access. 1803804Ssaidi@eecs.umich.edu regs = (size + 3) // 4 1813881Ssaidi@eecs.umich.edu subst = { "size" : size, "regs" : regs } 1823804Ssaidi@eecs.umich.edu memDecl = ''' 1833804Ssaidi@eecs.umich.edu union MemUnion { 1843804Ssaidi@eecs.umich.edu uint8_t bytes[%(size)d]; 1853804Ssaidi@eecs.umich.edu Element elements[%(size)d / sizeof(Element)]; 1863804Ssaidi@eecs.umich.edu uint32_t floatRegBits[%(regs)d]; 1873804Ssaidi@eecs.umich.edu }; 1883804Ssaidi@eecs.umich.edu ''' % subst 1893569Sgblack@eecs.umich.edu 1903569Sgblack@eecs.umich.edu # Do endian conversion for all the elements. 1913569Sgblack@eecs.umich.edu convCode = ''' 1923863Ssaidi@eecs.umich.edu const unsigned eCount = sizeof(memUnion.elements) / 1933863Ssaidi@eecs.umich.edu sizeof(memUnion.elements[0]); 1943804Ssaidi@eecs.umich.edu if (((CPSR)Cpsr).e) { 1953804Ssaidi@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 1963804Ssaidi@eecs.umich.edu memUnion.elements[i] = gtobe(memUnion.elements[i]); 1973804Ssaidi@eecs.umich.edu } 1983804Ssaidi@eecs.umich.edu } else { 1993804Ssaidi@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 2003804Ssaidi@eecs.umich.edu memUnion.elements[i] = gtole(memUnion.elements[i]); 2013804Ssaidi@eecs.umich.edu } 2023804Ssaidi@eecs.umich.edu } 2033569Sgblack@eecs.umich.edu ''' 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu # Offload everything into registers 2063804Ssaidi@eecs.umich.edu regSetCode = '' 2074070Ssaidi@eecs.umich.edu for reg in range(regs): 2084070Ssaidi@eecs.umich.edu mask = '' 2093804Ssaidi@eecs.umich.edu if reg == regs - 1: 2103804Ssaidi@eecs.umich.edu mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size)) 2113804Ssaidi@eecs.umich.edu regSetCode += ''' 2123804Ssaidi@eecs.umich.edu FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s; 2133804Ssaidi@eecs.umich.edu ''' % { "reg" : reg, "mask" : mask } 2143811Ssaidi@eecs.umich.edu 2153811Ssaidi@eecs.umich.edu # Pull everything in from registers 2163804Ssaidi@eecs.umich.edu regGetCode = '' 2173804Ssaidi@eecs.umich.edu for reg in range(regs): 2183863Ssaidi@eecs.umich.edu regGetCode += ''' 2193804Ssaidi@eecs.umich.edu memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw); 2203804Ssaidi@eecs.umich.edu ''' % { "reg" : reg } 2213804Ssaidi@eecs.umich.edu 2223804Ssaidi@eecs.umich.edu loadMemAccCode = convCode + regSetCode 2233804Ssaidi@eecs.umich.edu storeMemAccCode = regGetCode + convCode 2243804Ssaidi@eecs.umich.edu 2253804Ssaidi@eecs.umich.edu loadIop = InstObjParams('ldrneon%(size)d_uop' % subst, 2263811Ssaidi@eecs.umich.edu 'MicroLdrNeon%(size)dUop' % subst, 2273804Ssaidi@eecs.umich.edu 'MicroNeonMemOp', 2283804Ssaidi@eecs.umich.edu { 'mem_decl' : memDecl, 2293804Ssaidi@eecs.umich.edu 'size' : size, 2303804Ssaidi@eecs.umich.edu 'memacc_code' : loadMemAccCode, 2313804Ssaidi@eecs.umich.edu 'ea_code' : simdEnabledCheckCode + eaCode, 2323826Ssaidi@eecs.umich.edu 'predicate_test' : predicateTest }, 2333826Ssaidi@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) 2344070Ssaidi@eecs.umich.edu storeIop = InstObjParams('strneon%(size)d_uop' % subst, 2354070Ssaidi@eecs.umich.edu 'MicroStrNeon%(size)dUop' % subst, 2364070Ssaidi@eecs.umich.edu 'MicroNeonMemOp', 2374070Ssaidi@eecs.umich.edu { 'mem_decl' : memDecl, 2383804Ssaidi@eecs.umich.edu 'size' : size, 2393804Ssaidi@eecs.umich.edu 'memacc_code' : storeMemAccCode, 2403804Ssaidi@eecs.umich.edu 'ea_code' : simdEnabledCheckCode + eaCode, 2413804Ssaidi@eecs.umich.edu 'predicate_test' : predicateTest }, 2423804Ssaidi@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) 2433804Ssaidi@eecs.umich.edu 2443804Ssaidi@eecs.umich.edu exec_output += NeonLoadExecute.subst(loadIop) + \ 2453804Ssaidi@eecs.umich.edu NeonLoadInitiateAcc.subst(loadIop) + \ 2463804Ssaidi@eecs.umich.edu NeonLoadCompleteAcc.subst(loadIop) + \ 2473804Ssaidi@eecs.umich.edu NeonStoreExecute.subst(storeIop) + \ 2483804Ssaidi@eecs.umich.edu NeonStoreInitiateAcc.subst(storeIop) + \ 2493804Ssaidi@eecs.umich.edu NeonStoreCompleteAcc.subst(storeIop) 2503826Ssaidi@eecs.umich.edu header_output += MicroNeonMemDeclare.subst(loadIop) + \ 2513826Ssaidi@eecs.umich.edu MicroNeonMemDeclare.subst(storeIop) 2523826Ssaidi@eecs.umich.edu}}; 2533863Ssaidi@eecs.umich.edu 2543826Ssaidi@eecs.umich.edulet {{ 2553826Ssaidi@eecs.umich.edu exec_output = '' 2563826Ssaidi@eecs.umich.edu for eSize, type in (1, 'uint8_t'), \ 2573826Ssaidi@eecs.umich.edu (2, 'uint16_t'), \ 2583826Ssaidi@eecs.umich.edu (4, 'uint32_t'), \ 2593826Ssaidi@eecs.umich.edu (8, 'uint64_t'): 2603826Ssaidi@eecs.umich.edu size = eSize 2613826Ssaidi@eecs.umich.edu # An instruction handles no more than 16 bytes and no more than 2623826Ssaidi@eecs.umich.edu # 4 elements, or the number of elements needed to fill 8 or 16 bytes. 2633804Ssaidi@eecs.umich.edu sizes = set((16, 8)) 2643804Ssaidi@eecs.umich.edu for count in 1, 2, 3, 4: 2653804Ssaidi@eecs.umich.edu size = count * eSize 2663804Ssaidi@eecs.umich.edu if size <= 16: 2673804Ssaidi@eecs.umich.edu sizes.add(size) 2683804Ssaidi@eecs.umich.edu for size in sizes: 2693804Ssaidi@eecs.umich.edu substDict = { 2703863Ssaidi@eecs.umich.edu "class_name" : "MicroLdrNeon%dUop" % size, 2713863Ssaidi@eecs.umich.edu "targs" : type 2723863Ssaidi@eecs.umich.edu } 2733836Ssaidi@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2743836Ssaidi@eecs.umich.edu substDict["class_name"] = "MicroStrNeon%dUop" % size 2753804Ssaidi@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2763804Ssaidi@eecs.umich.edu size += eSize 2773863Ssaidi@eecs.umich.edu}}; 2783804Ssaidi@eecs.umich.edu 2793804Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2803804Ssaidi@eecs.umich.edu// 2813804Ssaidi@eecs.umich.edu// Neon (de)interlacing microops 2823804Ssaidi@eecs.umich.edu// 2833804Ssaidi@eecs.umich.edu 2843804Ssaidi@eecs.umich.edulet {{ 2853863Ssaidi@eecs.umich.edu header_output = exec_output = '' 2863804Ssaidi@eecs.umich.edu for dRegs in (2, 3, 4): 2873804Ssaidi@eecs.umich.edu loadConv = '' 2883804Ssaidi@eecs.umich.edu unloadConv = '' 2893804Ssaidi@eecs.umich.edu for dReg in range(dRegs): 2903804Ssaidi@eecs.umich.edu loadConv += ''' 2913881Ssaidi@eecs.umich.edu conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw); 2923804Ssaidi@eecs.umich.edu conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw); 2933804Ssaidi@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 2943804Ssaidi@eecs.umich.edu unloadConv += ''' 2953804Ssaidi@eecs.umich.edu FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]); 2963804Ssaidi@eecs.umich.edu FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]); 2973804Ssaidi@eecs.umich.edu ''' % { "dReg" : dReg } 2983804Ssaidi@eecs.umich.edu microDeintNeonCode = ''' 2993804Ssaidi@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3003863Ssaidi@eecs.umich.edu const unsigned regs = 2 * dRegs; 3013863Ssaidi@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3023836Ssaidi@eecs.umich.edu sizeof(Element); 3033804Ssaidi@eecs.umich.edu union convStruct { 3043804Ssaidi@eecs.umich.edu FloatRegBits cRegs[regs]; 3053804Ssaidi@eecs.umich.edu Element elements[dRegs * perDReg]; 3063881Ssaidi@eecs.umich.edu } conv1, conv2; 3073881Ssaidi@eecs.umich.edu 3083881Ssaidi@eecs.umich.edu %(loadConv)s 3093804Ssaidi@eecs.umich.edu 3103804Ssaidi@eecs.umich.edu unsigned srcElem = 0; 3113804Ssaidi@eecs.umich.edu for (unsigned destOffset = 0; 3123804Ssaidi@eecs.umich.edu destOffset < perDReg; destOffset++) { 3133804Ssaidi@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3143804Ssaidi@eecs.umich.edu conv2.elements[dReg * perDReg + destOffset] = 3153804Ssaidi@eecs.umich.edu conv1.elements[srcElem++]; 3163804Ssaidi@eecs.umich.edu } 3173804Ssaidi@eecs.umich.edu } 3183804Ssaidi@eecs.umich.edu 3193804Ssaidi@eecs.umich.edu %(unloadConv)s 3203804Ssaidi@eecs.umich.edu ''' % { "dRegs" : dRegs, 3213804Ssaidi@eecs.umich.edu "loadConv" : loadConv, 3223804Ssaidi@eecs.umich.edu "unloadConv" : unloadConv } 3233863Ssaidi@eecs.umich.edu microDeintNeonIop = \ 3243836Ssaidi@eecs.umich.edu InstObjParams('deintneon%duop' % (dRegs * 2), 3253804Ssaidi@eecs.umich.edu 'MicroDeintNeon%dUop' % (dRegs * 2), 3263804Ssaidi@eecs.umich.edu 'MicroNeonMixOp', 3273881Ssaidi@eecs.umich.edu { 'predicate_test': predicateTest, 3283881Ssaidi@eecs.umich.edu 'code' : microDeintNeonCode }, 3293881Ssaidi@eecs.umich.edu ['IsMicroop']) 3303804Ssaidi@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microDeintNeonIop) 3313804Ssaidi@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microDeintNeonIop) 3323804Ssaidi@eecs.umich.edu 3333804Ssaidi@eecs.umich.edu loadConv = '' 3343804Ssaidi@eecs.umich.edu unloadConv = '' 3353804Ssaidi@eecs.umich.edu for dReg in range(dRegs): 3363804Ssaidi@eecs.umich.edu loadConv += ''' 3373804Ssaidi@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw); 3383804Ssaidi@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw); 3393804Ssaidi@eecs.umich.edu ''' % { "dReg" : dReg } 3403804Ssaidi@eecs.umich.edu unloadConv += ''' 3413804Ssaidi@eecs.umich.edu FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]); 3423804Ssaidi@eecs.umich.edu FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]); 3433804Ssaidi@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 3443836Ssaidi@eecs.umich.edu microInterNeonCode = ''' 3453836Ssaidi@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3463881Ssaidi@eecs.umich.edu const unsigned regs = 2 * dRegs; 3473907Ssaidi@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3483804Ssaidi@eecs.umich.edu sizeof(Element); 3493881Ssaidi@eecs.umich.edu union convStruct { 3503881Ssaidi@eecs.umich.edu FloatRegBits cRegs[regs]; 3513804Ssaidi@eecs.umich.edu Element elements[dRegs * perDReg]; 3523907Ssaidi@eecs.umich.edu } conv1, conv2; 3533804Ssaidi@eecs.umich.edu 3543804Ssaidi@eecs.umich.edu %(loadConv)s 3553804Ssaidi@eecs.umich.edu 3563804Ssaidi@eecs.umich.edu unsigned destElem = 0; 3573804Ssaidi@eecs.umich.edu for (unsigned srcOffset = 0; 3583804Ssaidi@eecs.umich.edu srcOffset < perDReg; srcOffset++) { 3593881Ssaidi@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3603881Ssaidi@eecs.umich.edu conv2.elements[destElem++] = 3613881Ssaidi@eecs.umich.edu conv1.elements[dReg * perDReg + srcOffset]; 3623804Ssaidi@eecs.umich.edu } 3633881Ssaidi@eecs.umich.edu } 3643881Ssaidi@eecs.umich.edu 3653881Ssaidi@eecs.umich.edu %(unloadConv)s 3663881Ssaidi@eecs.umich.edu ''' % { "dRegs" : dRegs, 3673804Ssaidi@eecs.umich.edu "loadConv" : loadConv, 3683804Ssaidi@eecs.umich.edu "unloadConv" : unloadConv } 3693804Ssaidi@eecs.umich.edu microInterNeonIop = \ 3703804Ssaidi@eecs.umich.edu InstObjParams('interneon%duop' % (dRegs * 2), 3713804Ssaidi@eecs.umich.edu 'MicroInterNeon%dUop' % (dRegs * 2), 3723804Ssaidi@eecs.umich.edu 'MicroNeonMixOp', 3733881Ssaidi@eecs.umich.edu { 'predicate_test': predicateTest, 3743881Ssaidi@eecs.umich.edu 'code' : microInterNeonCode }, 3753804Ssaidi@eecs.umich.edu ['IsMicroop']) 3763881Ssaidi@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microInterNeonIop) 3773881Ssaidi@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microInterNeonIop) 3783881Ssaidi@eecs.umich.edu}}; 3793804Ssaidi@eecs.umich.edu 3803804Ssaidi@eecs.umich.edulet {{ 3813804Ssaidi@eecs.umich.edu exec_output = '' 3823804Ssaidi@eecs.umich.edu for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'): 3833804Ssaidi@eecs.umich.edu for dRegs in (2, 3, 4): 3843804Ssaidi@eecs.umich.edu Name = "MicroDeintNeon%dUop" % (dRegs * 2) 3853804Ssaidi@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3863804Ssaidi@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3873804Ssaidi@eecs.umich.edu Name = "MicroInterNeon%dUop" % (dRegs * 2) 3883804Ssaidi@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3893804Ssaidi@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3903804Ssaidi@eecs.umich.edu}}; 3913804Ssaidi@eecs.umich.edu 3923804Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 3933804Ssaidi@eecs.umich.edu// 3943804Ssaidi@eecs.umich.edu// Neon microops to pack/unpack a single lane 3953804Ssaidi@eecs.umich.edu// 3963804Ssaidi@eecs.umich.edu 3973804Ssaidi@eecs.umich.edulet {{ 3983804Ssaidi@eecs.umich.edu header_output = exec_output = '' 3994172Ssaidi@eecs.umich.edu for sRegs in 1, 2: 4003804Ssaidi@eecs.umich.edu baseLoadRegs = '' 4013804Ssaidi@eecs.umich.edu for reg in range(sRegs): 4023804Ssaidi@eecs.umich.edu baseLoadRegs += ''' 4033804Ssaidi@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); 4043804Ssaidi@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); 4053804Ssaidi@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4063804Ssaidi@eecs.umich.edu "reg1" : (2 * reg + 1) } 4073804Ssaidi@eecs.umich.edu for dRegs in range(sRegs, 5): 4083804Ssaidi@eecs.umich.edu unloadRegs = '' 4093804Ssaidi@eecs.umich.edu loadRegs = baseLoadRegs 4103804Ssaidi@eecs.umich.edu for reg in range(dRegs): 4113804Ssaidi@eecs.umich.edu loadRegs += ''' 4123804Ssaidi@eecs.umich.edu destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw); 4134172Ssaidi@eecs.umich.edu destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw); 4143804Ssaidi@eecs.umich.edu ''' % { "reg" : reg } 4153804Ssaidi@eecs.umich.edu unloadRegs += ''' 4163826Ssaidi@eecs.umich.edu FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4173826Ssaidi@eecs.umich.edu FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4183826Ssaidi@eecs.umich.edu ''' % { "reg" : reg } 4193916Ssaidi@eecs.umich.edu microUnpackNeonCode = ''' 4203916Ssaidi@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4213916Ssaidi@eecs.umich.edu sizeof(Element); 4224172Ssaidi@eecs.umich.edu 4233826Ssaidi@eecs.umich.edu union SourceRegs { 4243804Ssaidi@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4253804Ssaidi@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4263804Ssaidi@eecs.umich.edu } sourceRegs; 4273804Ssaidi@eecs.umich.edu 4283804Ssaidi@eecs.umich.edu union DestReg { 4293811Ssaidi@eecs.umich.edu FloatRegBits fRegs[2]; 4303811Ssaidi@eecs.umich.edu Element elements[perDReg]; 4313804Ssaidi@eecs.umich.edu } destRegs[%(dRegs)d]; 4323804Ssaidi@eecs.umich.edu 4333804Ssaidi@eecs.umich.edu %(loadRegs)s 4343804Ssaidi@eecs.umich.edu 4353826Ssaidi@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4363826Ssaidi@eecs.umich.edu destRegs[i].elements[lane] = sourceRegs.elements[i]; 4373826Ssaidi@eecs.umich.edu } 4383826Ssaidi@eecs.umich.edu 4393826Ssaidi@eecs.umich.edu %(unloadRegs)s 4403826Ssaidi@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 4413804Ssaidi@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 4423804Ssaidi@eecs.umich.edu 4433804Ssaidi@eecs.umich.edu microUnpackNeonIop = \ 4443811Ssaidi@eecs.umich.edu InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2), 4453811Ssaidi@eecs.umich.edu 'MicroUnpackNeon%dto%dUop' % 4463804Ssaidi@eecs.umich.edu (sRegs * 2, dRegs * 2), 4474172Ssaidi@eecs.umich.edu 'MicroNeonMixLaneOp', 4483804Ssaidi@eecs.umich.edu { 'predicate_test': predicateTest, 4493804Ssaidi@eecs.umich.edu 'code' : microUnpackNeonCode }, 4503836Ssaidi@eecs.umich.edu ['IsMicroop']) 4513826Ssaidi@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop) 4523826Ssaidi@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop) 4533826Ssaidi@eecs.umich.edu 4543826Ssaidi@eecs.umich.edu for sRegs in 1, 2: 4553826Ssaidi@eecs.umich.edu loadRegs = '' 4563826Ssaidi@eecs.umich.edu for reg in range(sRegs): 4573804Ssaidi@eecs.umich.edu loadRegs += ''' 4583804Ssaidi@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); 4593804Ssaidi@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); 4603804Ssaidi@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4614172Ssaidi@eecs.umich.edu "reg1" : (2 * reg + 1) } 4623833Ssaidi@eecs.umich.edu for dRegs in range(sRegs, 5): 4633836Ssaidi@eecs.umich.edu unloadRegs = '' 4643836Ssaidi@eecs.umich.edu for reg in range(dRegs): 4653836Ssaidi@eecs.umich.edu unloadRegs += ''' 4663836Ssaidi@eecs.umich.edu FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4673836Ssaidi@eecs.umich.edu FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4683836Ssaidi@eecs.umich.edu ''' % { "reg" : reg } 4693836Ssaidi@eecs.umich.edu microUnpackAllNeonCode = ''' 4703836Ssaidi@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4713836Ssaidi@eecs.umich.edu sizeof(Element); 4723836Ssaidi@eecs.umich.edu 4733836Ssaidi@eecs.umich.edu union SourceRegs { 4743836Ssaidi@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4753836Ssaidi@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4763836Ssaidi@eecs.umich.edu } sourceRegs; 4773836Ssaidi@eecs.umich.edu 4783836Ssaidi@eecs.umich.edu union DestReg { 4793836Ssaidi@eecs.umich.edu FloatRegBits fRegs[2]; 4803836Ssaidi@eecs.umich.edu Element elements[perDReg]; 4813836Ssaidi@eecs.umich.edu } destRegs[%(dRegs)d]; 4823836Ssaidi@eecs.umich.edu 4833836Ssaidi@eecs.umich.edu %(loadRegs)s 4843836Ssaidi@eecs.umich.edu 4853836Ssaidi@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4863833Ssaidi@eecs.umich.edu for (unsigned j = 0; j < perDReg; j++) 4873833Ssaidi@eecs.umich.edu destRegs[i].elements[j] = sourceRegs.elements[i]; 4883833Ssaidi@eecs.umich.edu } 4893833Ssaidi@eecs.umich.edu 4903833Ssaidi@eecs.umich.edu %(unloadRegs)s 4913833Ssaidi@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 4923833Ssaidi@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 4933833Ssaidi@eecs.umich.edu 4943833Ssaidi@eecs.umich.edu microUnpackAllNeonIop = \ 4953804Ssaidi@eecs.umich.edu InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2), 4963804Ssaidi@eecs.umich.edu 'MicroUnpackAllNeon%dto%dUop' % 4973804Ssaidi@eecs.umich.edu (sRegs * 2, dRegs * 2), 4983804Ssaidi@eecs.umich.edu 'MicroNeonMixOp', 4993804Ssaidi@eecs.umich.edu { 'predicate_test': predicateTest, 5003833Ssaidi@eecs.umich.edu 'code' : microUnpackAllNeonCode }, 5013833Ssaidi@eecs.umich.edu ['IsMicroop']) 5023811Ssaidi@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop) 5033804Ssaidi@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop) 5043804Ssaidi@eecs.umich.edu 5053804Ssaidi@eecs.umich.edu for dRegs in 1, 2: 5063804Ssaidi@eecs.umich.edu unloadRegs = '' 5073804Ssaidi@eecs.umich.edu for reg in range(dRegs): 5083804Ssaidi@eecs.umich.edu unloadRegs += ''' 5093804Ssaidi@eecs.umich.edu FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]); 5103833Ssaidi@eecs.umich.edu FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]); 5113804Ssaidi@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 5123804Ssaidi@eecs.umich.edu "reg1" : (2 * reg + 1) } 5133833Ssaidi@eecs.umich.edu for sRegs in range(dRegs, 5): 5143836Ssaidi@eecs.umich.edu loadRegs = '' 5153836Ssaidi@eecs.umich.edu for reg in range(sRegs): 5163836Ssaidi@eecs.umich.edu loadRegs += ''' 5173836Ssaidi@eecs.umich.edu sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw); 5183804Ssaidi@eecs.umich.edu sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw); 5193804Ssaidi@eecs.umich.edu ''' % { "reg" : reg } 5203804Ssaidi@eecs.umich.edu microPackNeonCode = ''' 5213836Ssaidi@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 5223836Ssaidi@eecs.umich.edu sizeof(Element); 5233804Ssaidi@eecs.umich.edu 5243804Ssaidi@eecs.umich.edu union SourceReg { 5253804Ssaidi@eecs.umich.edu FloatRegBits fRegs[2]; 5263804Ssaidi@eecs.umich.edu Element elements[perDReg]; 5273804Ssaidi@eecs.umich.edu } sourceRegs[%(sRegs)d]; 5283804Ssaidi@eecs.umich.edu 5293804Ssaidi@eecs.umich.edu union DestRegs { 5303804Ssaidi@eecs.umich.edu FloatRegBits fRegs[2 * %(dRegs)d]; 5313804Ssaidi@eecs.umich.edu Element elements[%(dRegs)d * perDReg]; 5323804Ssaidi@eecs.umich.edu } destRegs; 5333804Ssaidi@eecs.umich.edu 5343804Ssaidi@eecs.umich.edu %(loadRegs)s 5353833Ssaidi@eecs.umich.edu 5363836Ssaidi@eecs.umich.edu for (unsigned i = 0; i < %(sRegs)d; i++) { 5373804Ssaidi@eecs.umich.edu destRegs.elements[i] = sourceRegs[i].elements[lane]; 5383804Ssaidi@eecs.umich.edu } 5393804Ssaidi@eecs.umich.edu 5403804Ssaidi@eecs.umich.edu %(unloadRegs)s 5413804Ssaidi@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 5423804Ssaidi@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 5433804Ssaidi@eecs.umich.edu 5443916Ssaidi@eecs.umich.edu microPackNeonIop = \ 5453804Ssaidi@eecs.umich.edu InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2), 5463804Ssaidi@eecs.umich.edu 'MicroPackNeon%dto%dUop' % 5473804Ssaidi@eecs.umich.edu (sRegs * 2, dRegs * 2), 5483804Ssaidi@eecs.umich.edu 'MicroNeonMixLaneOp', 5493804Ssaidi@eecs.umich.edu { 'predicate_test': predicateTest, 5503804Ssaidi@eecs.umich.edu 'code' : microPackNeonCode }, 5513804Ssaidi@eecs.umich.edu ['IsMicroop']) 5523804Ssaidi@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop) 5533928Ssaidi@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microPackNeonIop) 5543804Ssaidi@eecs.umich.edu}}; 5553804Ssaidi@eecs.umich.edu 5563804Ssaidi@eecs.umich.edulet {{ 5573804Ssaidi@eecs.umich.edu exec_output = '' 5583836Ssaidi@eecs.umich.edu for type in ('uint8_t', 'uint16_t', 'uint32_t'): 5593836Ssaidi@eecs.umich.edu for sRegs in 1, 2: 5603836Ssaidi@eecs.umich.edu for dRegs in range(sRegs, 5): 5613836Ssaidi@eecs.umich.edu for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", 5623836Ssaidi@eecs.umich.edu "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", 5633826Ssaidi@eecs.umich.edu "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): 5643836Ssaidi@eecs.umich.edu Name = format % { "sRegs" : sRegs * 2, 5653836Ssaidi@eecs.umich.edu "dRegs" : dRegs * 2 } 5663804Ssaidi@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 5673804Ssaidi@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 5683804Ssaidi@eecs.umich.edu}}; 5693804Ssaidi@eecs.umich.edu 5703804Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 5713804Ssaidi@eecs.umich.edu// 5723804Ssaidi@eecs.umich.edu// Integer = Integer op Immediate microops 5733804Ssaidi@eecs.umich.edu// 5743804Ssaidi@eecs.umich.edu 5754172Ssaidi@eecs.umich.edulet {{ 5763836Ssaidi@eecs.umich.edu microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 5773836Ssaidi@eecs.umich.edu 'MicroIntImmOp', 5783836Ssaidi@eecs.umich.edu {'code': 'URa = URb + imm;', 5793836Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 5803836Ssaidi@eecs.umich.edu ['IsMicroop']) 5813836Ssaidi@eecs.umich.edu 5823833Ssaidi@eecs.umich.edu microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', 5833836Ssaidi@eecs.umich.edu 'MicroIntRegOp', 5843836Ssaidi@eecs.umich.edu {'code': 5853836Ssaidi@eecs.umich.edu '''URa = URb + shift_rm_imm(URc, shiftAmt, 5863929Ssaidi@eecs.umich.edu shiftType, 5873929Ssaidi@eecs.umich.edu CondCodes<29:>); 5883929Ssaidi@eecs.umich.edu ''', 5893836Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 5903836Ssaidi@eecs.umich.edu ['IsMicroop']) 5913836Ssaidi@eecs.umich.edu 5923836Ssaidi@eecs.umich.edu microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 5933836Ssaidi@eecs.umich.edu 'MicroIntImmOp', 5943836Ssaidi@eecs.umich.edu {'code': 'URa = URb - imm;', 5953836Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 5963836Ssaidi@eecs.umich.edu ['IsMicroop']) 5973836Ssaidi@eecs.umich.edu 5983836Ssaidi@eecs.umich.edu microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', 5994090Ssaidi@eecs.umich.edu 'MicroIntRegOp', 6004090Ssaidi@eecs.umich.edu {'code': 6014090Ssaidi@eecs.umich.edu '''URa = URb - shift_rm_imm(URc, shiftAmt, 6024090Ssaidi@eecs.umich.edu shiftType, 6034090Ssaidi@eecs.umich.edu CondCodes<29:>); 6044090Ssaidi@eecs.umich.edu ''', 6054090Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 6064090Ssaidi@eecs.umich.edu ['IsMicroop']) 6074090Ssaidi@eecs.umich.edu 6084090Ssaidi@eecs.umich.edu microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', 6094090Ssaidi@eecs.umich.edu 'MicroIntMov', 6104090Ssaidi@eecs.umich.edu {'code': 'IWRa = URb;', 6114090Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 6124090Ssaidi@eecs.umich.edu ['IsMicroop']) 6134090Ssaidi@eecs.umich.edu 6144090Ssaidi@eecs.umich.edu microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet', 6154090Ssaidi@eecs.umich.edu 'MicroIntMov', 6164090Ssaidi@eecs.umich.edu {'code': microRetUopCode % 'URb', 6174090Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 6184090Ssaidi@eecs.umich.edu ['IsMicroop', 'IsNonSpeculative', 6194090Ssaidi@eecs.umich.edu 'IsSerializeAfter']) 6204090Ssaidi@eecs.umich.edu 6214090Ssaidi@eecs.umich.edu setPCCPSRDecl = ''' 6224090Ssaidi@eecs.umich.edu CPSR cpsrOrCondCodes = URc; 6234090Ssaidi@eecs.umich.edu SCTLR sctlr = Sctlr; 6244090Ssaidi@eecs.umich.edu pNPC = URa; 6254090Ssaidi@eecs.umich.edu uint32_t newCpsr = 6264090Ssaidi@eecs.umich.edu cpsrWriteByInstr(cpsrOrCondCodes, URb, 6274090Ssaidi@eecs.umich.edu 0xF, true, sctlr.nmfi); 6284090Ssaidi@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 6293836Ssaidi@eecs.umich.edu NextThumb = ((CPSR)newCpsr).t; 6303833Ssaidi@eecs.umich.edu NextJazelle = ((CPSR)newCpsr).j; 6313833Ssaidi@eecs.umich.edu NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) 6323833Ssaidi@eecs.umich.edu | (((CPSR)URb).it1 & 0x3); 6333833Ssaidi@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 6343833Ssaidi@eecs.umich.edu ''' 6353833Ssaidi@eecs.umich.edu 6363833Ssaidi@eecs.umich.edu microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', 6373833Ssaidi@eecs.umich.edu 'MicroSetPCCPSR', 6383916Ssaidi@eecs.umich.edu {'code': setPCCPSRDecl, 6393833Ssaidi@eecs.umich.edu 'predicate_test': predicateTest}, 6403804Ssaidi@eecs.umich.edu ['IsMicroop']) 6413832Ssaidi@eecs.umich.edu 6423832Ssaidi@eecs.umich.edu header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ 6433804Ssaidi@eecs.umich.edu MicroIntImmDeclare.subst(microSubiUopIop) + \ 6443804Ssaidi@eecs.umich.edu MicroIntRegDeclare.subst(microAddUopIop) + \ 6453804Ssaidi@eecs.umich.edu MicroIntRegDeclare.subst(microSubUopIop) + \ 6463833Ssaidi@eecs.umich.edu MicroIntMovDeclare.subst(microUopRegMovIop) + \ 6473833Ssaidi@eecs.umich.edu MicroIntMovDeclare.subst(microUopRegMovRetIop) + \ 6483804Ssaidi@eecs.umich.edu MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop) 6493804Ssaidi@eecs.umich.edu 6503804Ssaidi@eecs.umich.edu decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \ 6513804Ssaidi@eecs.umich.edu MicroIntImmConstructor.subst(microSubiUopIop) + \ 6523804Ssaidi@eecs.umich.edu MicroIntRegConstructor.subst(microAddUopIop) + \ 6533804Ssaidi@eecs.umich.edu MicroIntRegConstructor.subst(microSubUopIop) + \ 6543804Ssaidi@eecs.umich.edu MicroIntMovConstructor.subst(microUopRegMovIop) + \ 6553804Ssaidi@eecs.umich.edu MicroIntMovConstructor.subst(microUopRegMovRetIop) + \ 6563804Ssaidi@eecs.umich.edu MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop) 6573833Ssaidi@eecs.umich.edu 6583804Ssaidi@eecs.umich.edu exec_output = PredOpExecute.subst(microAddiUopIop) + \ 6593910Ssaidi@eecs.umich.edu PredOpExecute.subst(microSubiUopIop) + \ 6603804Ssaidi@eecs.umich.edu PredOpExecute.subst(microAddUopIop) + \ 6613910Ssaidi@eecs.umich.edu PredOpExecute.subst(microSubUopIop) + \ 6623804Ssaidi@eecs.umich.edu PredOpExecute.subst(microUopRegMovIop) + \ 6633804Ssaidi@eecs.umich.edu PredOpExecute.subst(microUopRegMovRetIop) + \ 6643804Ssaidi@eecs.umich.edu PredOpExecute.subst(microUopSetPCCPSRIop) 6653804Ssaidi@eecs.umich.edu 6663910Ssaidi@eecs.umich.edu}}; 6673910Ssaidi@eecs.umich.edu 6683804Ssaidi@eecs.umich.edulet {{ 6693804Ssaidi@eecs.umich.edu iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 6703804Ssaidi@eecs.umich.edu header_output = MacroMemDeclare.subst(iop) 6713804Ssaidi@eecs.umich.edu decoder_output = MacroMemConstructor.subst(iop) 6723910Ssaidi@eecs.umich.edu 6733910Ssaidi@eecs.umich.edu iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", []) 6743910Ssaidi@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 6753910Ssaidi@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 6763910Ssaidi@eecs.umich.edu 6773910Ssaidi@eecs.umich.edu iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) 6783910Ssaidi@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 6793910Ssaidi@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 6803910Ssaidi@eecs.umich.edu 6813910Ssaidi@eecs.umich.edu iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", []) 6823910Ssaidi@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 6833910Ssaidi@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 6843910Ssaidi@eecs.umich.edu 6853902Ssaidi@eecs.umich.edu iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", []) 6863804Ssaidi@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 6873926Ssaidi@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 6883804Ssaidi@eecs.umich.edu 6893804Ssaidi@eecs.umich.edu vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) 6903804Ssaidi@eecs.umich.edu header_output += MacroVFPMemDeclare.subst(vfpIop) 6913804Ssaidi@eecs.umich.edu decoder_output += MacroVFPMemConstructor.subst(vfpIop) 6923856Ssaidi@eecs.umich.edu}}; 6933804Ssaidi@eecs.umich.edu