Searched hist:14133 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | system.hh | 14133:f3e7e7c3803d Tue Aug 06 09:49:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | system.cc | 14133:f3e7e7c3803d Tue Aug 06 09:49:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | ArmSystem.py | 14133:f3e7e7c3803d Tue Aug 06 09:49:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | isa.hh | 14133:f3e7e7c3803d Tue Aug 06 09:49:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| H A D | isa.cc | 14133:f3e7e7c3803d Tue Aug 06 09:49:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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