| /gem5/src/arch/x86/ |
| H A D | pagetable.cc | 52 user(true), uncacheable(0), global(false), patBit(0),
58 bool uncacheable, bool read_only) :
60 user(true), uncacheable(uncacheable), global(false), patBit(0),
72 SERIALIZE_SCALAR(uncacheable);
87 UNSERIALIZE_SCALAR(uncacheable);
57 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only) argument
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| H A D | pagetable.hh | 85 bool uncacheable; member in struct:X86ISA::TlbEntry
98 bool uncacheable, bool read_only);
165 bool uncacheable() { return pte.pcd; } function in class:X86ISA::LongModePTE
166 void uncacheable(bool u) { pte.pcd = u ? 1 : 0; } function in class:X86ISA::LongModePTE
187 uncacheable(_uncacheable);
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| H A D | pagetable_walker.cc | 292 bool uncacheable = pte.pcd; local
353 entry.uncacheable = uncacheable;
374 entry.uncacheable = uncacheable;
414 entry.uncacheable = uncacheable;
435 entry.uncacheable = uncacheable;
465 entry.uncacheable
[all...] |
| H A D | tlb.cc | 258 // Force the access to be uncacheable.
411 if (entry->uncacheable)
|
| /gem5/src/arch/mips/ |
| H A D | pagetable.hh | 87 bool uncacheable, bool read_only)
90 if (uncacheable || read_only)
91 warn("MIPS TlbEntry does not support uncacheable"
86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only) argument
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| /gem5/src/arch/riscv/ |
| H A D | pagetable.hh | 87 bool uncacheable, bool read_only)
90 if (uncacheable || read_only)
91 warn("RISC-V TlbEntry does not support uncacheable"
86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only) argument
|
| /gem5/src/arch/alpha/ |
| H A D | pagetable.hh | 108 bool uncacheable, bool read_only)
121 if (uncacheable || read_only)
122 warn("Alpha TlbEntry does not support uncacheable"
107 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only) argument
|
| /gem5/src/arch/power/ |
| H A D | tlb.hh | 66 bool uncacheable, bool read_only)
69 if (uncacheable || read_only)
70 warn("Power TlbEntry does not support uncacheable"
65 TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only) argument
|
| /gem5/src/cpu/testers/memtest/ |
| H A D | memtest.cc | 226 bool uncacheable = random_mt.random(0, 100) < percentUncacheable; local
239 if (uncacheable) {
248 !uncacheable;
|
| /gem5/src/arch/sparc/ |
| H A D | pagetable.hh | 234 bool uncacheable, bool read_only)
241 if (!uncacheable) {
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only) argument
|
| /gem5/src/arch/arm/ |
| H A D | pagetable.hh | 151 bool uncacheable, bool read_only) :
157 ns(true), nstid(true), el(EL0), nonCacheable(uncacheable),
150 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only) argument
|
| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.cc | 157 bool uncacheable = tlb_entry->uncacheable; local
188 if (uncacheable)
|
| H A D | gpu_tlb.cc | 869 if (entry->uncacheable)
893 // Force the access to be uncacheable.
1220 if (local_entry->uncacheable) {
1473 if (local_entry->uncacheable)
|
| /gem5/configs/example/ |
| H A D | memtest.py | 97 parser.add_option("-u", "--uncacheable", type="int", default=10,
99 help="Target percentage of uncacheable accesses "
222 percent_uncacheable = options.uncacheable,
|
| /gem5/src/mem/ |
| H A D | multi_level_page_table.hh | 252 new_entry.reset(old_entry.paddr(), true, old_entry.uncacheable(),
|