Searched refs:timing (Results 1 - 25 of 28) sorted by relevance

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/gem5/src/cpu/minor/
H A Dfunc_unit.cc136 MinorFUTiming &timing = *(description.timings[i]); local
141 unsigned int num_lats = timing.srcRegsRelativeLats.size();
144 lats << timing.srcRegsRelativeLats[j];
152 "Adding extra timing decode pattern %d to FU"
154 i, timing.mask, timing.match, lats.str());
218 MinorFUTiming &timing = *timings[i]; local
220 if (timing.provides(inst->opClass()) &&
221 (mach_inst & timing.mask) == timing
[all...]
H A Dexecute.cc660 MinorFUTiming *timing = (!inst->isFault() ? local
664 (timing ? &(timing->srcRegsRelativeLats)
670 if (timing && timing->suppress) {
692 if (timing) {
694 timing->extraCommitLat;
696 timing->extraCommitLatExpr;
698 timing->extraAssumedLat;
1149 /* If true, this instruction will, subject to timing tweak
[all...]
H A Dcpu.cc99 system->getMemoryMode() != Enums::timing)
102 "'timing' mode.\n");
240 "'timing' mode.\n");
/gem5/src/arch/arm/
H A Dstage2_lookup.hh67 bool timing; member in class:ArmISA::Stage2LookUp
81 transState(_transState), mode(_mode), timing(_timing),
H A Dstage2_lookup.cc60 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
186 timing, functional, false, tranType);
196 } else if (timing) {
H A Dtlb.hh236 Translation *translation, bool timing, bool functional,
241 Translation *translation, bool timing,
356 bool timing, ArmTranslationType tranType, bool functional = false);
358 Translation *translation, bool &delay, bool timing);
H A Dtable_walker.cc139 stage2Tran(nullptr), timing(false), functional(false),
203 // once per TLB. For timing mode, a new instance is generated for every
210 // If we are mixing functional mode with timing (or even
251 currState->timing = _timing;
326 if (!currState->timing) {
335 // If this was a functional non-timing access restore state to
523 if (currState->timing) {
691 if (currState->timing) {
875 if (currState->timing) {
963 if (currState->timing) {
[all...]
H A Dtlb.cc566 Translation *translation, bool &delay, bool timing)
1037 Translation *translation, bool &delay, bool timing,
1040 // No such thing as a functional timing access
1041 assert(!(timing && functional));
1142 Fault fault = getResultTe(&te, req, tc, mode, translation, timing,
1453 Translation *translation, bool timing, bool functional,
1496 translation, timing, functional, is_secure,
1498 // for timing mode, return and wait for table walk,
1499 if (timing || fault != NoFault) {
1521 Translation *translation, bool timing, boo
565 translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) argument
1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument
1452 getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) argument
1519 getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) argument
[all...]
H A Dtable_walker.hh776 /** If the mode is timing or atomic */
777 bool timing; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
795 /** Whether the response is delayed in timing mode due to additional
846 /** If a timing translation is currently in progress */
909 bool timing, bool functional, bool secure,
/gem5/src/mem/ruby/system/
H A DRubySystem.py49 store and only use ruby for timing.")
/gem5/src/dev/x86/
H A Dintdev.hh116 sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing) argument
120 if (timing) {
122 // The target handles cleaning up the packet in timing mode.
/gem5/src/arch/x86/
H A Dpagetable_walker.hh111 bool timing; member in class:X86ISA::Walker::WalkerState
121 functional(_isFunctional), timing(false),
147 // State for timing and atomic accesses (need multiple per walker in
148 // the case of multiple outstanding requests in timing mode)
H A Dtlb.hh113 bool &delayedResponse, bool timing);
H A Dpagetable_walker.cc73 // TODO: in timing mode, instead of blocking when there are other
187 timing = _isTiming;
234 if (timing) {
707 return timing;
H A Dtlb.cc271 Mode mode, bool &delayedResponse, bool timing)
353 if (timing || fault != NoFault) {
269 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) argument
/gem5/configs/splash2/
H A Drun.py49 parser.add_option("-t", "--timing", action="store_true")
183 if options.timing:
276 if options.timing or options.detailed:
277 root.system.mem_mode = 'timing'
H A Dcluster.py50 parser.add_option("-t", "--timing", action="store_true")
170 if options.timing:
291 if options.timing or options.detailed:
292 root.system.mem_mode = 'timing'
/gem5/src/gpu-compute/
H A DGPU.py154 timing = Param.Bool(False, 'timing memory accesses') variable in class:Shader
H A Dgpu_tlb.hh184 bool timing, int &latency);
H A Dshader.cc58 timingSim(p->timing), hsail_mode(SIMT),
/gem5/ext/dsent/
H A DDSENT.cc81 // Currently we can only optimize timing at the top level
105 cout << "Report timing:" << endl;
110 double timing = timing_tree.performCritPathExtract(electrical_model->getNet(net_name)); local
111 cout << net_name << " = " << timing << endl;
160 // Perform timing optimization if needed
168 // Report timing if needed
/gem5/util/cxx_config/
H A Dmain.cc296 system.setMemoryMode(Enums::timing);
/gem5/util/systemc/gem5_within_systemc/
H A Dmain.cc440 system.setMemoryMode(Enums::timing);
/gem5/src/sim/
H A Dsystem.hh104 { panic("SystemPort does not receive timing!\n"); return false; }
151 * Is the system in timing mode?
157 return memoryMode == Enums::timing;
186 * @param mode Mode to change to (atomic/timing/...)
/gem5/src/python/m5/
H A Dsimulate.py69 "timing" : objects.params.timing,

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