Searched refs:regFile (Results 1 - 6 of 6) sorted by relevance

/gem5/src/cpu/o3/
H A Dfree_list.cc41 : _name(_my_name), regFile(_regFile)
47 regFile->initFreeList(this);
H A Drename_map.cc118 regFile = _regFile;
145 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
151 auto range = this->regFile->getRegElemIds(vr);
161 regFile->numVecElemPhysRegs() -
165 auto range = regFile->getRegIds(VecRegClass);
185 PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
211 dst[l] = regFile->readVecElem(s_prid);
217 regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
H A Dcpu.cc115 regFile(params->numPhysIntRegs,
122 freeList(name() + ".freelist", &regFile),
127 regFile.totalNumPhysRegs()),
233 commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
237 renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
1202 return regFile.readIntReg(phys_reg);
1210 return regFile.readFloatReg(phys_reg);
1219 return regFile.readVecReg(phys_reg);
1228 return regFile.getWritableVecReg(phys_reg);
1236 return regFile
[all...]
H A Drename_map.hh202 PhysRegFile *regFile; member in class:UnifiedRenameMap
209 UnifiedRenameMap() : regFile(nullptr) {};
294 return regFile->getMiscRegId(arch_reg.flatIndex());
H A Dcpu.hh381 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
392 return regFile.readVecLane<VecElem>(phys_reg);
401 return regFile.setVecLane(phys_reg, val);
578 PhysRegFile regFile; member in class:FullO3CPU
H A Dfree_list.hh150 PhysRegFile *regFile; member in class:UnifiedFreeList

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