Searched refs:pkt (Results 1 - 25 of 375) sorted by relevance

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/gem5/src/arch/sparc/
H A Dmmapped_ipr.hh49 handleIprRead(ThreadContext *xc, Packet *pkt) argument
51 if (GenericISA::isGenericIprAccess(pkt))
52 return GenericISA::handleGenericIprRead(xc, pkt);
54 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
58 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
60 if (GenericISA::isGenericIprAccess(pkt))
61 return GenericISA::handleGenericIprWrite(xc, pkt);
63 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
/gem5/src/mem/protocol/
H A Dfunctional.cc51 FunctionalResponseProtocol *peer, PacketPtr pkt) const
53 assert(pkt->isRequest());
54 return peer->recvFunctional(pkt);
61 FunctionalRequestProtocol *peer, PacketPtr pkt) const
63 assert(pkt->isRequest());
64 return peer->recvFunctionalSnoop(pkt);
H A Dtiming.cc50 TimingRequestProtocol::sendReq(TimingResponseProtocol *peer, PacketPtr pkt) argument
52 assert(pkt->isRequest());
53 return peer->recvTimingReq(pkt);
58 TimingResponseProtocol *peer, PacketPtr pkt) const
60 assert(pkt->isRequest());
61 return peer->tryTiming(pkt);
66 TimingResponseProtocol *peer, PacketPtr pkt)
68 assert(pkt->isResponse());
69 return peer->recvTimingSnoopResp(pkt);
81 TimingResponseProtocol::sendResp(TimingRequestProtocol *peer, PacketPtr pkt) argument
65 sendSnoopResp( TimingResponseProtocol *peer, PacketPtr pkt) argument
88 sendSnoopReq( TimingRequestProtocol *peer, PacketPtr pkt) argument
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H A Datomic.cc52 AtomicRequestProtocol::send(AtomicResponseProtocol *peer, PacketPtr pkt) argument
54 assert(pkt->isRequest());
55 return peer->recvAtomic(pkt);
60 PacketPtr pkt, MemBackdoorPtr &backdoor)
62 assert(pkt->isRequest());
63 return peer->recvAtomicBackdoor(pkt, backdoor);
69 AtomicResponseProtocol::sendSnoop(AtomicRequestProtocol *peer, PacketPtr pkt) argument
71 assert(pkt->isRequest());
72 return peer->recvAtomicSnoop(pkt);
59 sendBackdoor(AtomicResponseProtocol *peer, PacketPtr pkt, MemBackdoorPtr &backdoor) argument
H A Datomic.hh64 * @param pkt Packet to send.
68 Tick send(AtomicResponseProtocol *peer, PacketPtr pkt);
75 * @param pkt Packet to send.
81 Tick sendBackdoor(AtomicResponseProtocol *peer, PacketPtr pkt,
87 virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
101 * @param pkt Snoop packet to send.
105 Tick sendSnoop(AtomicRequestProtocol *peer, PacketPtr pkt);
110 virtual Tick recvAtomic(PacketPtr pkt) = 0;
117 PacketPtr pkt, MemBackdoorPtr &backdoor) = 0;
H A Dfunctional.hh62 * @param pkt Packet to send.
64 void send(FunctionalResponseProtocol *peer, PacketPtr pkt) const;
69 virtual void recvFunctionalSnoop(PacketPtr pkt) = 0;
82 * @param pkt Snoop packet to send.
84 void sendSnoop(FunctionalRequestProtocol *peer, PacketPtr pkt) const;
89 virtual void recvFunctional(PacketPtr pkt) = 0;
H A Dtiming.hh65 * @param pkt Packet to send.
69 bool sendReq(TimingResponseProtocol *peer, PacketPtr pkt);
79 * @param pkt Packet to send.
83 bool trySend(TimingResponseProtocol *peer, PacketPtr pkt) const;
92 * @param pkt Packet to send.
94 bool sendSnoopResp(TimingResponseProtocol *peer, PacketPtr pkt);
105 virtual bool recvTimingResp(PacketPtr pkt) = 0;
110 virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
139 * @param pkt Packet to send.
143 bool sendResp(TimingRequestProtocol *peer, PacketPtr pkt);
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/gem5/src/mem/
H A Dtport.cc54 SimpleTimingPort::recvFunctional(PacketPtr pkt) argument
56 if (!respQueue.trySatisfyFunctional(pkt)) {
58 recvAtomic(pkt);
63 SimpleTimingPort::recvTimingReq(PacketPtr pkt) argument
68 if (pkt->cacheResponding())
72 bool needsResponse = pkt->needsResponse();
73 Tick latency = recvAtomic(pkt);
78 assert(pkt->isResponse());
79 schedTimingResp(pkt, curTick() + latency);
82 pendingDelete.reset(pkt);
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H A Daddr_mapper.cc69 AddrMapper::recvFunctional(PacketPtr pkt) argument
71 Addr orig_addr = pkt->getAddr();
72 pkt->setAddr(remapAddr(orig_addr));
73 masterPort.sendFunctional(pkt);
74 pkt->setAddr(orig_addr);
78 AddrMapper::recvFunctionalSnoop(PacketPtr pkt) argument
80 Addr orig_addr = pkt->getAddr();
81 pkt->setAddr(remapAddr(orig_addr));
82 slavePort.sendFunctionalSnoop(pkt);
83 pkt
87 recvAtomic(PacketPtr pkt) argument
97 recvAtomicSnoop(PacketPtr pkt) argument
107 recvTimingReq(PacketPtr pkt) argument
135 recvTimingResp(PacketPtr pkt) argument
168 recvTimingSnoopReq(PacketPtr pkt) argument
174 recvTimingSnoopResp(PacketPtr pkt) argument
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H A Dhmc_controller.cc42 bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id) argument
48 assert(!pkt->isExpressSnoop());
58 src_port->name(), pkt->cmdString(), pkt->getAddr());
63 src_port->name(), pkt->cmdString(), pkt->getAddr());
67 unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
68 unsigned int pkt_cmd = pkt->cmdToIndex();
71 Tick old_header_delay = pkt
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H A Dsimple_mem.cc74 SimpleMemory::recvAtomic(PacketPtr pkt) argument
76 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
79 access(pkt);
84 SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor) argument
86 Tick latency = recvAtomic(pkt);
94 SimpleMemory::recvFunctional(PacketPtr pkt) argument
96 pkt->pushLabel(name());
98 functionalAccess(pkt);
104 done = pkt->trySatisfyFunctional(p->pkt);
112 recvTimingReq(PacketPtr pkt) argument
279 recvAtomic(PacketPtr pkt) argument
285 recvAtomicBackdoor( PacketPtr pkt, MemBackdoorPtr &_backdoor) argument
292 recvFunctional(PacketPtr pkt) argument
298 recvTimingReq(PacketPtr pkt) argument
[all...]
H A Dnoncoherent_xbar.cc102 NoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id) argument
108 assert(!pkt->isExpressSnoop());
111 PortID master_port_id = findPort(pkt->getAddrRange());
117 src_port->name(), pkt->cmdString(), pkt->getAddr());
122 src_port->name(), pkt->cmdString(), pkt->getAddr());
126 unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
127 unsigned int pkt_cmd = pkt
180 recvTimingResp(PacketPtr pkt, PortID master_port_id) argument
246 recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id, MemBackdoorPtr *backdoor) argument
286 recvFunctional(PacketPtr pkt, PortID slave_port_id) argument
[all...]
/gem5/src/dev/
H A Disa_fake.cc55 IsaFake::read(PacketPtr pkt) argument
57 pkt->makeAtomicResponse();
61 name(), pkt->getAddr(), pkt->getSize());
64 pkt->getAddr(), pkt->getSize());
65 pkt->setBadAddress();
67 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
69 pkt
94 write(PacketPtr pkt) argument
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/gem5/src/sim/probe/
H A Dmem.hh62 explicit PacketInfo(const PacketPtr& pkt) : argument
63 cmd(pkt->cmd),
64 addr(pkt->getAddr()),
65 size(pkt->getSize()),
66 flags(pkt->req->getFlags()),
67 pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
68 master(pkt->req->masterId()) { }
/gem5/src/dev/arm/
H A Damba.hh51 orderId(PacketPtr pkt) argument
53 return pkt->req->masterId();
H A Damba_fake.cc56 AmbaFake::read(PacketPtr pkt) argument
58 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
60 Addr daddr = pkt->getAddr() - pioAddr;
64 pkt->setLE<uint32_t>(0);
65 if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
68 pkt->makeAtomicResponse();
73 AmbaFake::write(PacketPtr pkt) argument
76 Addr daddr = pkt->getAddr() - pioAddr;
81 pkt
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H A Dsmmu_v3_ports.cc52 SMMUMasterPort::recvTimingResp(PacketPtr pkt) argument
54 return smmu.masterRecvTimingResp(pkt);
70 SMMUMasterTableWalkPort::recvTimingResp(PacketPtr pkt) argument
72 return smmu.masterTableWalkRecvTimingResp(pkt);
91 SMMUSlavePort::recvFunctional(PacketPtr pkt) argument
93 if (!respQueue.trySatisfyFunctional(pkt))
94 recvAtomic(pkt);
98 SMMUSlavePort::recvAtomic(PacketPtr pkt) argument
100 return ifc.recvAtomic(pkt);
104 SMMUSlavePort::recvTimingReq(PacketPtr pkt) argument
118 recvAtomic(PacketPtr pkt) argument
150 recvTimingResp(PacketPtr pkt) argument
163 recvFunctional(PacketPtr pkt) argument
169 recvAtomic(PacketPtr pkt) argument
175 recvTimingReq(PacketPtr pkt) argument
[all...]
/gem5/src/mem/qos/
H A Dpolicy.cc51 Policy::schedule(const PacketPtr pkt) argument
53 assert(pkt->req);
54 return schedule(pkt->req->masterId(), pkt->getSize());
/gem5/src/arch/generic/
H A Dmmapped_ipr.hh103 isGenericIprAccess(const Packet *pkt) argument
105 Request::Flags flags(pkt->req->getFlags());
114 * @param pkt Packet from the CPU
117 Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt);
122 * @param pkt Packet from the CPU
125 Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt);
135 * @param pkt Packet from the CPU
139 handleIprRead(ThreadContext *xc, Packet *pkt) argument
141 if (!isGenericIprAccess(pkt))
144 return handleGenericIprRead(xc, pkt);
160 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
[all...]
/gem5/src/dev/serial/
H A Dsimple.cc55 SimpleUart::read(PacketPtr pkt) argument
57 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
64 pkt->setUintX(data, byteOrder);
66 pkt->makeAtomicResponse();
71 SimpleUart::write(PacketPtr pkt) argument
74 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
76 uint8_t data = (uint8_t)pkt->getUintX(byteOrder);
82 pkt
[all...]
/gem5/src/mem/cache/
H A Dcache.cc81 Cache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, argument
84 BaseCache::satisfyRequest(pkt, blk);
86 if (pkt->isRead()) {
88 if (pkt->fromCache()) {
89 assert(pkt->getSize() == blkSize);
92 if (pkt->needsWritable()) {
94 assert(pkt->cmd == MemCmd::ReadExReq ||
95 pkt->cmd == MemCmd::SCUpgradeFailReq);
96 assert(!pkt->hasSharers());
101 pkt
164 access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) argument
270 recvTimingSnoopResp(PacketPtr pkt) argument
304 promoteWholeLineWrites(PacketPtr pkt) argument
316 handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) argument
327 handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time) argument
406 recvTimingReq(PacketPtr pkt) argument
540 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); local
566 handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) argument
658 recvAtomic(PacketPtr pkt) argument
689 serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) argument
889 PacketPtr pkt = (blk->isDirty() || writebackClean) ? local
912 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); local
936 PacketPtr pkt = req_pkt; local
971 handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, bool is_deferred, bool pending_inval) argument
1184 recvTimingSnoopReq(PacketPtr pkt) argument
1302 recvAtomicSnoop(PacketPtr pkt) argument
1315 isCachedAbove(PacketPtr pkt, bool is_timing) argument
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H A Dnoncoherent_cache.hh74 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
77 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
81 void recvTimingReq(PacketPtr pkt) override;
88 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
91 void recvTimingResp(PacketPtr pkt) override;
93 void recvTimingSnoopReq(PacketPtr pkt) override {
94 panic("Unexpected timing snoop request %s", pkt->print());
97 void recvTimingSnoopResp(PacketPtr pkt) override {
98 panic("Unexpected timing snoop response %s", pkt->print());
101 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBl
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H A Dnoncoherent_cache.cc73 NoncoherentCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) argument
78 assert(pkt->isRead() || pkt->isWrite());
79 BaseCache::satisfyRequest(pkt, blk);
83 NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, argument
86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
88 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) {
122 NoncoherentCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, argument
126 Addr blk_addr = pkt
138 recvTimingReq(PacketPtr pkt) argument
161 PacketPtr pkt = new Packet(cpu_pkt->req, MemCmd::ReadReq, blkSize); local
174 handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) argument
223 recvAtomic(PacketPtr pkt) argument
236 functionalAccess(PacketPtr pkt, bool from_cpu_side) argument
245 serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) argument
320 recvTimingResp(PacketPtr pkt) argument
351 PacketPtr pkt = (blk->isDirty() || writebackClean) ? local
[all...]
/gem5/src/learning_gem5/part2/
H A Dsimple_memobj.cc63 SimpleMemobj::CPUSidePort::sendPacket(PacketPtr pkt) argument
70 if (!sendTimingResp(pkt)) {
71 blockedPacket = pkt;
93 SimpleMemobj::CPUSidePort::recvFunctional(PacketPtr pkt) argument
96 return owner->handleFunctional(pkt);
100 SimpleMemobj::CPUSidePort::recvTimingReq(PacketPtr pkt) argument
103 if (!owner->handleRequest(pkt)) {
118 PacketPtr pkt = blockedPacket; local
122 sendPacket(pkt);
126 SimpleMemobj::MemSidePort::sendPacket(PacketPtr pkt) argument
139 recvTimingResp(PacketPtr pkt) argument
152 PacketPtr pkt = blockedPacket; local
166 handleRequest(PacketPtr pkt) argument
185 handleResponse(PacketPtr pkt) argument
212 handleFunctional(PacketPtr pkt) argument
[all...]
/gem5/src/arch/x86/
H A Dmmapped_ipr.hh58 handleIprRead(ThreadContext *xc, Packet *pkt) argument
60 if (GenericISA::isGenericIprAccess(pkt)) {
61 return GenericISA::handleGenericIprRead(xc, pkt);
63 Addr offset = pkt->getAddr() & mask(3);
65 pkt->getAddr() / sizeof(RegVal));
68 assert(offset + pkt->getSize() <= sizeof(RegVal));
69 pkt->setData(((uint8_t *)&data) + offset);
75 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
77 if (GenericISA::isGenericIprAccess(pkt)) {
78 return GenericISA::handleGenericIprWrite(xc, pkt);
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