1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "dev/serial/simple.hh"
41
42#include "mem/packet.hh"
43#include "mem/packet_access.hh"
44#include "params/SimpleUart.hh"
45#include "sim/sim_exit.hh"
46
47SimpleUart::SimpleUart(const SimpleUartParams *p)
48    : Uart(p, p->pio_size),
49      byteOrder(p->big_endian ? BigEndianByteOrder : LittleEndianByteOrder),
50      endOnEOT(p->end_on_eot)
51{
52}
53
54Tick
55SimpleUart::read(PacketPtr pkt)
56{
57    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
58
59    uint64_t data = 0;
60
61    if (device->dataAvailable())
62        data = device->readData();
63
64    pkt->setUintX(data, byteOrder);
65
66    pkt->makeAtomicResponse();
67    return pioDelay;
68}
69
70Tick
71SimpleUart::write(PacketPtr pkt)
72{
73
74    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
75
76    uint8_t data = (uint8_t)pkt->getUintX(byteOrder);
77    if (data == 0x04 && endOnEOT)
78        exitSimLoop("UART received EOT", 0);
79
80    device->writeData(data);
81
82    pkt->makeAtomicResponse();
83    return pioDelay;
84}
85
86SimpleUart *
87SimpleUartParams::create()
88{
89    return new SimpleUart(this);
90}
91