Searched refs:numSrcRegs (Results 1 - 11 of 11) sorted by relevance

/gem5/src/cpu/
H A Dbase_dyn_inst_impl.hh209 seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
210 if (++readyRegs == numSrcRegs()) {
232 for (int i = 1; i < numSrcRegs(); ++i) {
H A Dstatic_inst.hh102 /// See numSrcRegs().
133 int8_t numSrcRegs() const { return _numSrcRegs; } function in class:StaticInst
219 /// Only the entries from 0 through numSrcRegs()-1 are valid.
H A Dbase_dyn_inst.hh584 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } function in class:BaseDynInst
/gem5/src/cpu/minor/
H A Dscoreboard.cc163 unsigned int num_srcs = staticInst->numSrcRegs();
228 unsigned int num_srcs = staticInst->numSrcRegs();
H A Ddyn_inst.cc189 unsigned int num_src_regs = staticInst->numSrcRegs();
/gem5/src/arch/arm/insts/
H A Dmisc.cc53 for (unsigned i = 0; i < numSrcRegs(); i++) {
/gem5/src/cpu/o3/
H A Dinst_queue_impl.hh1277 src_reg_idx < squashed_inst->numSrcRegs();
1372 int8_t total_src_regs = new_inst->numSrcRegs();
H A Ddecode_impl.hh700 if (inst->numSrcRegs() == 0) {
H A Drename_impl.hh1070 unsigned num_src_regs = inst->numSrcRegs();
/gem5/src/arch/
H A Disa_parser.py1195 self.numSrcRegs = 0
1213 op_desc.src_reg_idx = self.numSrcRegs
1214 self.numSrcRegs += 1
1240 if parser.maxInstSrcRegs < self.numSrcRegs:
1241 parser.maxInstSrcRegs = self.numSrcRegs
/gem5/src/cpu/o3/probe/
H A Delastic_trace.cc244 int8_t max_regs = dyn_inst->numSrcRegs();

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