Searched refs:isStage2 (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/
H A Dtlb.cc78 isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
106 if (stage2Mmu && !isStage2)
265 if (!isStage2 && isHyp) {
296 if (!isStage2 && !hyp) {
371 assert(!isStage2);
398 if (!isStage2 &&
588 ArmFault::AlignmentFault, isStage2,
627 if (isStage2 && req->isPTWalk() && hcr.ptw &&
632 isStage2, tranMethod);
643 ArmFault::AlignmentFault, isStage2,
[all...]
H A Dtable_walker.cc62 isStage2(p->is_stage2), tlb(NULL),
121 if (!isStage2) {
236 if (isStage2) {
268 if (isStage2) {
308 currState->stage2Req = _stage2Req && !isStage2;
310 bool long_desc_format = currState->aarch64 || _isHyp || isStage2 ||
391 currState->isHyp || isStage2)
459 assert(currState->sctlr.m || isStage2);
477 isStage2,
484 ArmFault::TranslationLL + L1, isStage2,
[all...]
H A Dfaults.hh235 virtual bool isStage2() const { return false; } function in class:ArmISA::ArmFault
450 bool isStage2() const override { return stage2; }
H A Dtlb.hh153 bool isStage2; // Indicates this TLB is part of the second stage MMU member in class:ArmISA::TLB
H A Disa.cc1777 newVal |= armFault->isStage2() ? 0x200 : 0;
2036 newVal |= armFault->isStage2() ? 0x200 : 0;
2041 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
2042 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
H A Dtable_walker.hh836 const bool isStage2; member in class:ArmISA::TableWalker::LongDescriptor

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