Searched refs:isLoad (Results 1 - 25 of 39) sorted by relevance

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/gem5/ext/dsent/model/timing_graph/
H A DElectricalLoad.cc49 bool ElectricalLoad::isLoad() const function in class:DSENT::ElectricalLoad
H A DElectricalLoad.h51 bool isLoad() const;
H A DElectricalTimingNode.h68 virtual bool isLoad() const;
H A DElectricalTimingNode.cc102 bool ElectricalTimingNode::isLoad() const function in class:DSENT::ElectricalTimingNode
/gem5/src/cpu/
H A Dinteltrace.cc53 if (staticInst->isLoad()) {
/gem5/src/gpu-compute/
H A Dglobal_memory_pipeline.cc73 if ((m) && (m->isLoad() || m->isAtomicRet())) {
100 if (m->isLoad() || m->isAtomic()) {
116 if (mp->isLoad() || mp->isAtomic()) {
178 if (gpuDynInst->isLoad() || gpuDynInst->isAtomic()) {
187 if (gpuDynInst->isLoad() || gpuDynInst->isAtomic()) {
216 if (gpuDynInst->isLoad() || gpuDynInst->isAtomic()) {
H A Dlocal_memory_pipeline.cc67 if ((m) && (m->isLoad() || m->isAtomicRet())) {
93 if (m->isLoad() || m->isAtomic()) {
H A Dwavefront.cc191 ii->isALU() || (ii->isKernArgSeg() && ii->isLoad()))) {
354 ii->isALU() || ii->isLoad() || ii->isStore() || ii->isAtomic() ||
398 (ii->isKernArgSeg() && ii->isLoad()) ||
416 if (ii->isLoad() || ii->isAtomic() || ii->isMemFence()) {
455 if (ii->isLoad() || ii->isAtomic() || ii->isMemFence()) {
554 (ii->isKernArgSeg() && ii->isLoad()) || ii->isArgSeg() ||
564 } else if (ii->isLoad() && ii->isFlat()) {
594 } else if (ii->isLoad() && ii->isGlobalMem()) {
616 } else if (ii->isLoad() && ii->isLocalMem()) {
704 (ii->isKernArgSeg() && ii->isLoad()) ||
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H A Dgpu_dyn_inst.cc241 GPUDynInst::isLoad() const function in class:GPUDynInst
243 return _staticInst->isLoad();
H A Dlds_state.cc145 if (gpuDynInst->isLoad() || gpuDynInst->isStore()) {
211 int busLength = (dynInst->isLoad()) ? parent->loadBusLength() :
H A Dgpu_static_inst.hh113 bool isLoad() const { return _flags[Load]; } function in class:GPUStaticInst
H A Dvector_register_file.cc156 bool loadInstr = ii->isLoad();
/gem5/src/cpu/o3/
H A Dlsq.hh84 outstanding(0), isLoad(isLoad_), needWB(isLoad_), isSplit(false),
98 bool isLoad; member in class:LSQ::LSQSenderState
305 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) : argument
311 flags.set(Flag::IsLoad, isLoad);
317 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument
331 flags.set(Flag::IsLoad, isLoad);
339 isLoad() const function
353 if (isLoad()) {
623 (isPartialFault() && isLoad()));
709 using LSQRequest::isLoad;
720 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, const Addr& addr, const uint32_t& size, const Request::Flags& flags_, PacketDataPtr data = nullptr, uint64_t* res = nullptr, AtomicOpFunctorPtr amo_op = nullptr) argument
779 SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, const Addr& addr, const uint32_t& size, const Request::Flags & flags_, PacketDataPtr data = nullptr, uint64_t* res = nullptr) argument
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H A Dlsq_impl.hh688 LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, argument
696 bool isAtomic M5_VAR_USED = !isLoad && amo_op;
716 req = new SplitDataRequest(&thread[tid], inst, isLoad, addr,
719 req = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
747 if (isLoad)
757 } else if (isLoad) {
981 this->isLoad() ? BaseTLB::Read : BaseTLB::Write);
1011 PacketPtr resp = isLoad()
1014 if (isLoad())
1033 isLoad()
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H A Dlsq_unit_impl.hh129 assert(inst->isLoad() || inst->isStoreConditional() ||
280 assert(inst->isLoad() || inst->isStore() || inst->isAtomic());
282 if (inst->isLoad()) {
474 if (inst->isLoad()) {
771 state->isLoad = false;
1057 LSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) argument
1065 lsq->cachePortAvailable(isLoad)) {
1075 if (!isLoad) {
1078 lsq->cachePortBusy(isLoad);
1086 if (!isLoad) {
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H A Dmem_dep_unit_impl.hh194 if ((inst->isLoad() || inst->isAtomic()) && loadBarrier) {
248 if (inst->isLoad()) {
262 } else if (inst->isLoad()) {
298 } else if (inst->isLoad()) {
H A Diew_impl.hh481 if (skidBuffer[tid].front()->isLoad()) {
866 if (insts[tid].front()->isLoad()) {
1009 if (inst->isLoad()) {
1039 (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1042 inst->isLoad() ? "LQ" : "SQ");
1075 } else if (inst->isLoad()) {
1283 } else if (inst->isLoad()) {
1367 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1658 if (inst->isLoad()) {
H A Dcpu.hh714 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, argument
721 return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
/gem5/src/cpu/minor/
H A Dlsq.cc64 isLoad(isLoad_),
180 os << (isLoad ? 'R' : 'W') << ';';
310 request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
557 if (!isLoad) {
568 makePacketForRequest(fragment, isLoad, this, request_data);
647 if (isLoad) {
690 if (isLoad) {
715 fragmentRequests[fragment_index], thread, this, (isLoad ?
809 assert(load->isLoad);
1027 bool is_load = request->isLoad;
1574 pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector<bool>& byteEnable) argument
1679 makePacketForRequest(const RequestPtr &request, bool isLoad, Packet::SenderState *sender_state, PacketDataPtr data) argument
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H A Dlsq.hh133 bool isLoad; member in class:Minor::LSQ::LSQRequest
709 Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
733 PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad,
/gem5/src/cpu/o3/probe/
H A Delastic_trace.cc321 if (head_inst->isLoad() && exec_info_ptr->executeTick != MaxTick &&
404 new_record->type = head_inst->isLoad() ? Record::LOAD :
441 if (head_inst->isLoad() && !commit) {
574 if (new_record->isLoad()) {
635 return(past_record->isLoad() && past_record->commit &&
644 return (past_record->isLoad() && past_record->commit &&
693 if (past_record->isLoad()) {
764 if (isLoad()) {
806 if (temp_ptr->isLoad() || temp_ptr->isStore()) {
815 if (temp_ptr->isLoad()) {
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H A Delastic_trace.hh305 bool isLoad() const { return (type == Record::LOAD); } function in struct:ElasticTrace::TraceInfo
/gem5/src/arch/arm/insts/
H A Dsve_macromem.hh355 bool isLoad = (__opClass == MemReadOp); local
356 assert(!firstFault || isLoad);
361 if (isLoad) {
373 if (isLoad) {
387 isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
459 bool isLoad = (__opClass == MemReadOp); local
460 assert(!firstFault || isLoad);
465 if (isLoad) {
477 if (isLoad) {
491 isLoad
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/gem5/src/cpu/trace/
H A Dtrace_cpu.cc482 } else if (node_ptr->isLoad() || node_ptr->isStore()) {
503 if (node_ptr->isLoad() && !node_ptr->isStrictlyOrdered()) {
559 if (!node_ptr->isLoad() || node_ptr->isStrictlyOrdered()) {
636 node_ptr->isLoad() ? ++numSOLoads : ++numSOStores;
673 if (node_ptr->isLoad()) {
900 if (new_node->isLoad()) {
937 if (done_node->isLoad()) {
992 if (new_node->isLoad() && numInFlightLoads >= sizeLoadBuffer) {
1439 if (isLoad() || isStore()) {
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.cc147 loadAccess(tarmCtx.staticInst->isLoad())

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