Searched refs:device_bus_width (Results 1 - 5 of 5) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py120 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
336 device_bus_width = 8 variable in class:DDR3_1600_8x8
432 device_bus_width = 32 variable in class:HMC_2500_1x32
545 device_bus_width = 4 variable in class:DDR4_2400_16x4
653 device_bus_width = 8 variable in class:DDR4_2400_8x8
680 device_bus_width = 16 variable in class:DDR4_2400_4x16
729 device_bus_width = 32 variable in class:LPDDR2_S4_1066_1x32
828 device_bus_width = 128 variable in class:WideIO_200_1x128
897 device_bus_width = 32 variable in class:LPDDR3_1600_1x32
994 device_bus_width variable in class:GDDR5_4000_2x32
121 "device/chip") variable in class:DRAMCtrl
1081 device_bus_width = 128 variable in class:HBM_1000_4H_1x128
1170 device_bus_width = 64 variable in class:HBM_1000_4H_1x64
[all...]
H A Ddrampower.cc63 archSpec.width = p->device_bus_width;
H A Ddram_ctrl.cc69 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
/gem5/configs/dram/
H A Dsweep.py146 system.mem_ctrls[0].device_bus_width.value *
H A Dlow_power_sweep.py146 system.mem_ctrls[0].device_bus_width.value *

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