/gem5/src/sim/ |
H A D | sim_exit.hh | 39 Tick curTick(); 49 /// Python) at the end of the current cycle (curTick()). The message 53 Tick when = curTick(), Tick repeat = 0,
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H A D | stat_control.hh | 62 * checkpoint, curTick will be updated, and any already scheduled events can 77 void schedStatEvent(bool dump, bool reset, Tick when = curTick(),
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H A D | simulate.cc | 107 inform("Entering event queue @ %d. Starting simulation...\n", curTick()); 109 if (num_cycles < MaxTick - curTick()) 110 num_cycles = curTick() + num_cycles; 122 quantum_event = new GlobalSyncEvent(curTick() + simQuantum, simQuantum, 190 assert(curTick() <= eventq->nextTick() &&
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H A D | debug.cc | 96 schedBreak(curTick() + delta); 114 when = curTick() + 1;
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H A D | stat_control.cc | 81 startTick = curTick(); 98 return curTick() - startTick; 104 return curTick(); 240 Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat); 275 * by curTick. This ensures that we do not schedule the event is the past. 279 if (period >= curTick()) { 282 schedStatEvent(true, true, (Tick)period + curTick(), (Tick)period); 293 * shift the event by curTick. 296 (dumpEvent->scheduled() && dumpEvent->when() < curTick())) { 297 // shift by curTick() an [all...] |
H A D | clocked_object.hh | 69 // the tick value of the next clock edge (>= curTick()) at the 79 * complete, tick must be at least curTick(). 86 // has already passed curTick() 87 if (tick >= curTick()) 96 if (tick >= curTick()) 102 Cycles elapsedCycles(divCeil(curTick() - tick, clockPeriod())); 142 Cycles elapsedCycles(divCeil(curTick(), clockPeriod())); 168 * curTick() is on a clock edge, the number of cycles in the parameter is 169 * added to curTick() to be returned. When curTick() i [all...] |
H A D | clocked_object.cc | 93 if (prvEvalTick == curTick() && curTick() != 0) { 113 Tick elapsed_time = curTick() - prvEvalTick; 124 prvEvalTick = curTick(); 136 Tick elapsed_time = curTick() - prvEvalTick;
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H A D | sim_events.cc | 67 : GlobalEvent(curTick(), Minimum_Pri, IsExitEvent), 85 schedule(curTick() + repeat); 93 warn_if(serialize && (when != curTick() || repeat),
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H A D | core.hh | 47 inline Tick curTick() { return _curEventQueue->getCurTick(); } function
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/gem5/src/mem/ruby/structures/ |
H A D | BankedArray.cc | 61 if (busyBanks[bank].endAccess >= curTick()) { 77 if (busyBanks[bank].endAccess >= curTick()) { 78 if (busyBanks[bank].startAccess == curTick() && 89 busyBanks[bank].startAccess = curTick(); 90 busyBanks[bank].endAccess = curTick() + 59 assert(bank < banks); if (busyBanks[bank].endAccess >= curTick()) argument 75 assert(bank < banks); if (busyBanks[bank].endAccess >= curTick()) argument
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/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/ |
H A D | feeder.cc | 51 schedule(&event, curTick() + delay); 62 schedule(&event, curTick() + delay);
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/gem5/configs/learning_gem5/part2/ |
H A D | hello_goodbye.py | 59 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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H A D | run_simple.py | 57 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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/gem5/src/python/m5/ |
H A D | __init__.py | 41 _m5.core.curTick
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H A D | event.py | 78 self.eventq.schedule(self, m5.curTick() + self.period) 81 print("Progress! Time now %fs" % (m5.curTick()/1e12)) 82 self.eventq.schedule(self, m5.curTick() + self.period)
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/gem5/src/mem/cache/replacement_policies/ |
H A D | bip_rp.cc | 51 casted_replacement_data->lastTouchTick = curTick();
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/gem5/src/unittest/ |
H A D | stattest.cc | 423 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 498 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 500 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 502 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 504 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 506 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 513 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 515 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 517 curEventQueue()->setCurTick(curTick() + ULL(1000000)); 519 curEventQueue()->setCurTick(curTick() [all...] |
/gem5/src/base/ |
H A D | trace.hh | 172 Trace::getDebugLogger()->dump(curTick(), name(), data, count); \ 178 Trace::getDebugLogger()->dprintf(curTick(), name(), \ 186 Trace::getDebugLogger()->dprintf(curTick(), s->name(), \ 200 Trace::getDebugLogger()->dump(curTick(), name(), data, count); \ 204 Trace::getDebugLogger()->dprintf(curTick(), name(), __VA_ARGS__); \
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/gem5/src/learning_gem5/part2/ |
H A D | hello_object.cc | 69 schedule(event, curTick() + latency);
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H A D | goodbye_object.cc | 91 schedule(event, curTick() + bandwidth * bytes_copied); 95 exitSimLoop(buffer, 0, curTick() + bandwidth * bytes_copied);
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/gem5/src/mem/cache/ |
H A D | cache_blk.cc | 62 tickInserted = curTick();
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/gem5/src/mem/cache/prefetch/ |
H A D | sbooe.cc | 78 if (entry.expectedArrivalTick > curTick()) { 84 sb.insert(access_line, curTick() + averageAccessLatency); 100 // (2) Calculate the elapsed cycles until it was filled (curTick) 107 Tick elapsed_ticks = curTick() - it->second; 133 demandAddresses.insert(std::pair<Addr, Tick>(pfi_addr, curTick()));
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/gem5/src/mem/ |
H A D | tport.cc | 79 schedTimingResp(pkt, curTick() + latency);
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/gem5/src/dev/ |
H A D | mc146818.cc | 133 schedule(event, curTick() + event.offset); 135 schedule(tickEvent, curTick() + tickEvent.offset); 184 schedule(tickEvent, curTick() + SimClock::Int::s / 2); 282 Tick rtcTimerInterruptTickOffset = event.when() - curTick(); 284 Tick rtcClockTickOffset = tickEvent.when() - curTick(); 321 parent->schedule(this, curTick() + interval); 328 parent->schedule(this, curTick() + interval); 342 parent->schedule(this, curTick() + SimClock::Int::s);
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/gem5/src/dev/net/ |
H A D | etherdump.cc | 97 pkthdr.seconds = curTick() / SimClock::Int::s; 98 pkthdr.microseconds = (curTick() / SimClock::Int::us) % ULL(1000000);
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