Searched refs:computeUnit (Results 1 - 25 of 35) sorted by relevance

12

/gem5/src/gpu-compute/
H A Dwavefront.cc299 return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs();
315 if (!computeUnit->AllAtBarrier(barrierId,barrierCnt,
316 computeUnit->getRefCounter(dispatchId, wgId))) {
331 for (int j=0; j < computeUnit->numGlbMemUnits; ++j) {
332 if (computeUnit->vrfToGlobalMemPipeBus[j].prerdy())
334 if (computeUnit->wfWait[j].prerdy())
341 for (int j=0; j < computeUnit->numLocMemUnits; ++j) {
342 if (computeUnit->vrfToLocalMemPipeBus[j].prerdy())
344 if (computeUnit->wfWait[j].prerdy())
360 computeUnit
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H A Dcondition_register_state.cc45 computeUnit = nullptr;
53 computeUnit = _computeUnit;
54 _name = computeUnit->name() + ".CondRegState";
73 uint32_t pipeLen = w->computeUnit->spBypassLength();
76 w->computeUnit->
79 w->computeUnit->shader->tick_cnt +
80 w->computeUnit->shader->ticks(pipeLen), 0);
H A Dlocal_memory_pipeline.cc46 computeUnit(nullptr), lmQueueSize(p->local_mem_queue_size)
53 computeUnit = cu;
54 _name = computeUnit->name() + ".LocalMemPipeline";
71 w->computeUnit->vrf[w->simdId]->
77 computeUnit->locMemToVrfBus.rdy() && (computeUnit->shader->coissue_return
78 || computeUnit->wfWait.at(m->pipeId).rdy())) {
86 computeUnit->shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
89 computeUnit->shader->ScheduleAdd(&w->outstandingReqsWrLm,
94 computeUnit
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H A Dfetch_unit.cc54 computeUnit(nullptr),
69 computeUnit = cu;
70 timingSim = computeUnit->shader->timingSim;
72 fetchStatusQueue.resize(computeUnit->shader->n_wf);
74 for (int j = 0; j < computeUnit->shader->n_wf; ++j) {
85 for (int j = 0; j < computeUnit->shader->n_wf; ++j) {
133 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
137 int block_size = computeUnit->cacheLineSize();
150 computeUnit->masterId(), 0, 0, nullptr);
165 computeUnit
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H A Dglobal_memory_pipeline.cc48 computeUnit(nullptr), gmQueueSize(p->global_mem_queue_size),
57 computeUnit = cu;
58 globalMemSize = computeUnit->shader->globalMemSize;
59 _name = computeUnit->name() + ".GlobalMemPipeline";
77 w->computeUnit->vrf[w->simdId]->
81 if (m && m->latency.rdy() && computeUnit->glbMemToVrfBus.rdy() &&
83 (computeUnit->shader->coissue_return ||
84 computeUnit->wfWait.at(m->pipeId).rdy())) {
93 computeUnit->shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
96 computeUnit
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H A Dscoreboard_check_stage.cc68 computeUnit = cu;
69 _name = computeUnit->name() + ".ScoreboardCheckStage";
72 readyList.push_back(&computeUnit->readyList[unitId]);
76 waveStatusList.push_back(&computeUnit->waveStatusList[unitId]);
79 vectorAluInstAvail = &computeUnit->vectorAluInstAvail;
80 glbMemInstAvail= &computeUnit->glbMemInstAvail;
81 shrMemInstAvail= &computeUnit->shrMemInstAvail;
141 for (int wvId = 0; wvId < computeUnit->shader->n_wf; ++wvId) {
151 if (computeUnit->cedeSIMD(unitId, wvId)) {
155 readyList[computeUnit
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H A Dexec_stage.cc56 computeUnit = cu;
57 _name = computeUnit->name() + ".ExecStage";
58 dispatchList = &computeUnit->dispatchList;
59 vectorAluInstAvail = &(computeUnit->vectorAluInstAvail);
60 glbMemInstAvail= &(computeUnit->glbMemInstAvail);
61 shrMemInstAvail= &(computeUnit->shrMemInstAvail);
70 if (computeUnit->isVecAlu(unitId) && vectorAluInstAvail->at(unitId)) {
76 if (computeUnit->isGlbMem(unitId) && *glbMemInstAvail > 0) {
83 if (computeUnit->isShrMem(unitId) && *shrMemInstAvail > 0) {
H A Dfetch_stage.cc43 computeUnit(nullptr)
59 computeUnit = cu;
60 _name = computeUnit->name() + ".FetchStage";
63 fetchUnit[j].bindWaveList(&computeUnit->wfList[j]);
64 fetchUnit[j].init(computeUnit);
H A Dvector_register_state.cc42 VecRegisterState::VecRegisterState() : computeUnit(nullptr)
51 computeUnit = _computeUnit;
52 _name = computeUnit->name() + ".VecRegState";
H A Dschedule_stage.cc63 computeUnit = cu;
64 _name = computeUnit->name() + ".ScheduleStage";
67 scheduler[j].bindList(&computeUnit->readyList[j]);
71 waveStatusList.push_back(&computeUnit->waveStatusList[j]);
74 dispatchList = &computeUnit->dispatchList;
101 if (computeUnit->vrf[simdId]->
126 uint32_t readyListSize = computeUnit->readyList[j].size();
142 assert(computeUnit->readyList[j].size() == readyListSize - 1);
H A Dgpu_exec_context.hh51 ComputeUnit* computeUnit();
H A Dvector_register_file.cc72 computeUnit = _computeUnit;
73 vgprState->setParent(computeUnit);
180 computeUnit->spBypassLength() :
181 computeUnit->dpBypassLength();
184 computeUnit->registerEvent(w->simdId, physReg,
186 computeUnit->shader->tick_cnt +
187 computeUnit->shader->ticks(pipeLen),
206 computeUnit->registerEvent(w->simdId, regVec[i], operandSize,
207 computeUnit->shader->tick_cnt + timestamp +
208 computeUnit
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H A Dfetch_unit.hh69 ComputeUnit *computeUnit; member in class:FetchUnit
H A Dfetch_stage.hh71 ComputeUnit *computeUnit; member in class:FetchStage
H A Dschedule_stage.hh70 ComputeUnit *computeUnit; member in class:ScheduleStage
H A Dgpu_exec_context.cc45 GPUExecContext::computeUnit() function in class:GPUExecContext
H A Dgpu_dyn_inst.cc45 : GPUExecContext(_cu, _wf), addr(computeUnit()->wfSize(), (Addr)0),
49 tlbHitLevel.assign(computeUnit()->wfSize(), -1);
50 d_data = new uint8_t[computeUnit()->wfSize() * 16];
51 a_data = new uint8_t[computeUnit()->wfSize() * 8];
52 x_data = new uint8_t[computeUnit()->wfSize() * 8];
53 for (int i = 0; i < (computeUnit()->wfSize() * 8); ++i) {
57 for (int i = 0; i < (computeUnit()->wfSize() * 16); ++i) {
H A Dcompute_unit.cc633 computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId];
638 computeUnit->cu_id, w->simdId, w->wfSlotId,
641 computeUnit->shader->dispatcher->notifyWgCompl(w);
648 computeUnit->cu_id, gpuDynInst->simdId,
673 computeUnit->memPort[index]->createMemRespEvent(pkt);
676 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
679 computeUnit->schedule(mem_resp_event,
680 curTick() + computeUnit->resp_tick_latency);
695 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
714 computeUnit
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H A Dlocal_memory_pipeline.hh89 ComputeUnit *computeUnit; member in class:LocalMemPipeline
H A Dscoreboard_check_stage.hh79 ComputeUnit *computeUnit; member in class:ScoreboardCheckStage
/gem5/src/arch/hsail/insts/
H A Dmem_impl.hh63 addr_vec.resize(w->computeUnit->wfSize(), (Addr)0);
66 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
134 return w->wfSlotId * w->privSizePerItem * w->computeUnit->wfSize() +
135 se->offset * w->computeUnit->wfSize() +
152 Addr ret = addr_div8 * 8 * w->computeUnit->wfSize() + lane * 8 +
156 (w->privSizePerItem * w->computeUnit->wfSize()));
190 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
199 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
238 m->cu_id = w->computeUnit->cu_id;
239 m->latency.init(&w->computeUnit
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H A Dpseudo_inst.cc87 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
185 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
191 disassemble(), w->computeUnit->cu_id, w->simdId,
195 disassemble(), w->computeUnit->cu_id, w->simdId,
208 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
214 disassemble(), w->computeUnit->cu_id, w->simdId,
218 disassemble(), w->computeUnit->cu_id, w->simdId,
234 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
273 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
314 for (int lane = 0; lane < w->computeUnit
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H A Dmain.cc137 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
155 int32_t refCount = w->computeUnit->getLds().
159 w->computeUnit->cu_id, w->wgId, refCount);
162 w->computeUnit->vectorRegsReserved[w->simdId] -=
165 assert(w->computeUnit->vectorRegsReserved[w->simdId] >= 0);
169 w->computeUnit->vrf[w->simdId]->numRegs();
171 w->computeUnit->vrf[w->simdId]->manager->
176 w->computeUnit->completedWfs++;
179 w->computeUnit->cu_id, w->simdId, w->wfSlotId, w->wfDynId);
193 w->computeUnit
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H A Dmem.hh443 for (int i = 0; i < gpuDynInst->computeUnit()->wfSize(); ++i)
453 [k * gpuDynInst->computeUnit()->wfSize()];
455 for (int i = 0; i < gpuDynInst->computeUnit()->wfSize(); ++i) {
466 gpuDynInst->computeUnit()->masterId(),
473 if (gpuDynInst->computeUnit()->shader->
489 gpuDynInst->computeUnit()->sendRequest(gpuDynInst,
545 &((c1*)gpuDynInst->d_data)[k * w->computeUnit->wfSize()];
547 for (int i = 0; i < w->computeUnit->wfSize(); ++i) {
551 "ld inst)\n", w->computeUnit->cu_id, w->simdId,
556 w->computeUnit
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/gem5/src/arch/hsail/
H A Doperand.hh167 ret = (w->computeUnit->vrf[w->simdId]->
172 ret = (w->computeUnit->vrf[w->simdId]->
177 ret = w->computeUnit->vrf[w->simdId]->
205 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
210 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
218 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
222 w->computeUnit->vrf[w->simdId]->write<uint32_t>(vgprIdx, val, lane);
268 return w->computeUnit->vrf[w->simdId]->read<OperandType>(vgprIdx,lane);
276 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
283 w->computeUnit
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