arch/hsail/operand.hh

167               ret = (w->computeUnit->vrf[w->simdId]->
172               ret = (w->computeUnit->vrf[w->simdId]->
177               ret = w->computeUnit->vrf[w->simdId]->
205             w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
210     w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
218             w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
222     w->computeUnit->vrf[w->simdId]->write<uint32_t>(vgprIdx, val, lane);
268         return w->computeUnit->vrf[w->simdId]->read<OperandType>(vgprIdx,lane);
276                 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
283         w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
337                 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
369             return (OperandType)w->computeUnit->wfSize();
676     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
733     for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane)
782                 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane,