/gem5/ext/dsent/model/std_cells/ |
H A D | BUF.cc | 87 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 89 // Standard cell cache string 93 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 94 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 95 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 98 getAreaResult("Active")->setValue(cache->get(cell_name + "->ActiveArea")); 99 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->ActiveArea")); 113 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 115 // Stadard cell cache string 125 leakage += cache 158 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | INV.cc | 95 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 97 // Standard cell cache string 101 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 102 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 103 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 106 getAreaResult("Active")->setValue(cache->get(cell_name + "->Area->Active")); 107 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->Area->Metal1Wire")); 121 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 123 // Standard cell cache string 133 leakage += cache 176 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | AND2.cc | 100 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 102 // Standard cell cache string 106 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 107 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 108 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 109 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 110 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 113 getAreaResult("Active")->setValue(cache->get(cell_name + "->ActiveArea")); 114 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->ActiveArea")); 128 Map<double>* cache local 210 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | NAND2.cc | 102 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 104 // Standard cell cache string 108 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 109 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 110 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 111 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 112 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 115 getAreaResult("Active")->setValue(cache->get(cell_name + "->Area->Active")); 116 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->Area->Active")); 125 Map<double>* cache local 206 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | NOR2.cc | 102 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 104 // Standard cell cache string 108 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 109 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 110 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 111 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 112 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 115 getAreaResult("Active")->setValue(cache->get(cell_name + "->ActiveArea")); 116 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->ActiveArea")); 125 Map<double>* cache local 205 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | MUX2.cc | 106 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 108 // Standard cell cache string 112 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 113 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 114 getLoad("S0_Cap")->setLoadCap(cache->get(cell_name + "->Cap->S0")); 116 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 117 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 118 getDelay("S0_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->S0_to_Y")); 120 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 123 getAreaResult("Active")->setValue(cache 138 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 239 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | XOR2.cc | 99 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 101 // Standard cell cache string 105 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 106 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 108 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 109 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 111 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 114 getAreaResult("Active")->setValue(cache->get(cell_name + "->ActiveArea")); 115 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->ActiveArea")); 129 Map<double>* cache local 220 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | LATQ.cc | 103 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 105 // Standard cell cache string 109 getLoad("D_Cap")->setLoadCap(cache->get(cell_name + "->Cap->D")); 110 getLoad("G_Cap")->setLoadCap(cache->get(cell_name + "->Cap->G")); 111 getDriver("Q_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Q")); 112 getDelay("G_to_Q_delay")->setDelay(cache->get(cell_name + "->Delay->G_to_Q")); 113 getDelay("D_to_Q_delay")->setDelay(cache->get(cell_name + "->Delay->D_to_Q")); 116 getAreaResult("Active")->setValue(cache->get(cell_name + "->Area->Active")); 117 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->Area->Metal1Wire")); 131 Map<double>* cache local 230 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | OR2.cc | 95 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 97 // Standard cell cache string 101 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 102 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 103 getDelay("A_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_Y")); 104 getDelay("B_to_Y_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_Y")); 105 getDriver("Y_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Y")); 108 getAreaResult("Active")->setValue(cache->get(cell_name + "->ActiveArea")); 109 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->ActiveArea")); 123 Map<double>* cache local 201 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | DFFQ.cc | 109 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 111 // Standard cell cache string 115 getLoad("D_Cap")->setLoadCap(cache->get(cell_name + "->Cap->D")); 116 getLoad("CK_Cap")->setLoadCap(cache->get(cell_name + "->Cap->CK")); 117 getDriver("Q_Ron")->setOutputRes(cache->get(cell_name + "->DriveRes->Q")); 118 getDelay("CK_to_Q_delay")->setDelay(cache->get(cell_name + "->Delay->CK_to_Q")); 119 getDelay("D_Setup_delay")->setDelay(cache->get(cell_name + "->Delay->D_Setup")); 122 getAreaResult("Active")->setValue(cache->get(cell_name + "->Area->Active")); 123 getAreaResult("Metal1Wire")->setValue(cache->get(cell_name + "->Area->Metal1Wire")); 137 Map<double>* cache local 275 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
H A D | ADDF.cc | 126 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 128 // Standard cell cache string 132 getLoad("A_Cap")->setLoadCap(cache->get(cell_name + "->Cap->A")); 133 getLoad("B_Cap")->setLoadCap(cache->get(cell_name + "->Cap->B")); 134 getLoad("CI_Cap")->setLoadCap(cache->get(cell_name + "->Cap->CI")); 136 getDelay("A_to_S_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_S")); 137 getDelay("B_to_S_delay")->setDelay(cache->get(cell_name + "->Delay->B_to_S")); 138 getDelay("CI_to_S_delay")->setDelay(cache->get(cell_name + "->Delay->CI_to_S")); 139 getDelay("A_to_CO_delay")->setDelay(cache->get(cell_name + "->Delay->A_to_CO")); 140 getDelay("B_to_CO_delay")->setDelay(cache 162 Map<double>* cache = getTechModel()->getStdCellLib()->getStdCellCache(); local 334 Map<double>* cache = cell_lib_->getStdCellCache(); local [all...] |
/gem5/src/base/ |
H A D | addr_range_map.hh | 146 cache.remove(p); 154 cache.remove(p); 162 cache.erase(cache.begin(), cache.end()); 204 * Add an address range map entry to the cache. 212 // If there's a cache, add this element to it. 213 if (cache.size() >= max_cache_size) { 214 // If the cache is full, move the last element to the 217 auto last = cache [all...] |
/gem5/src/mem/ruby/system/ |
H A D | WeightedLRUReplacementPolicy.py | 42 cache = Param.RubyCache("") variable in class:WeightedLRUReplacementPolicy
|
/gem5/configs/ruby/ |
H A D | Garnet_standalone.py | 72 # Only one cache exists for this protocol, so by default use the L1D 75 cache = L1Cache(size = options.l1d_size, 79 # Only one unified L1 cache exists. Can cache instructions and data. 82 cacheMemory = cache, 85 cpu_seq = RubySequencer(icache = cache, 86 dcache = cache,
|
/gem5/configs/learning_gem5/part2/ |
H A D | simple_cache.py | 31 World application. Adds a simple cache between the CPU and the membus. 62 # Create a simple cache 63 system.cache = SimpleCache(size='1kB') 65 # Connect the I and D cache ports of the CPU to the memobj. 68 system.cpu.icache_port = system.cache.cpu_side 69 system.cpu.dcache_port = system.cache.cpu_side 71 # Hook the cache up to the memory bus 72 system.cache.mem_side = system.membus.slave
|
/gem5/src/mem/cache/prefetch/ |
H A D | base.cc | 49 #include "mem/cache/prefetch/base.hh" 55 #include "mem/cache/base.hh" 93 : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size), 106 assert(!cache); 107 cache = _cache; 109 // If the cache has a different block size from the system's, save it 110 blkSize = cache->getBlockSize(); 151 return cache->inCache(addr, is_secure); 157 return cache->inMissQueue(addr, is_secure); 163 return cache [all...] |
/gem5/ext/sst/tests/ |
H A D | test6_arm_4c.py | 110 cache = sst.Component(name, "memHierarchy.Cache") 111 cache.addParams(baseCacheParams) 112 cache.addParams(l1CacheParams) 114 link.connect((m5, connector, lat), (cache, "high_network_0", lat)) 115 return cache
|
/gem5/configs/example/ |
H A D | memtest.py | 57 # arbitrarily deep cache hierarchies, sharing or no sharing of caches, 75 # memory. Each cache then fans out to a subtree. The last integer in 80 # cache string as there should always be testers attached to the 84 help="Colon-separated cache hierarchy specification, " 87 parser.add_option("--noncoherent-cache", action="store_true", 88 help="Adds a non-coherent, last-level cache") 182 # Define a prototype L1 cache that we scale for all successive levels 195 # Now add additional cache levels (if any) by scaling L1 params, the 237 # Recursive function to create a sub-tree of the cache and tester 279 subsys.cache [all...] |
H A D | memcheck.py | 75 # it is possible to create a system with arbitrarily deep cache 82 # caches/testers closest to main memory. Each cache then fans out to a 87 # should have one element more than the cache string as there should 97 help="Colon-separated cache hierarchy specification, " 161 print("Error: Must have at least one cache per level") 168 # Define a prototype L1 cache that we scale for all successive levels 185 # Now add additional cache levels (if any) by scaling L1 params, the 234 # Recursive function to create a sub-tree of the cache and tester 271 subsys.cache = tester_caches + tree_caches 272 for cache i [all...] |
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/ |
H A D | amoadd_d.S | 26 # try again after a cache miss
|
H A D | amoadd_w.S | 26 # try again after a cache miss
|
H A D | amoand_d.S | 26 # try again after a cache miss
|
H A D | amoand_w.S | 26 # try again after a cache miss
|
H A D | amoor_d.S | 26 # try again after a cache miss
|
H A D | amoor_w.S | 26 # try again after a cache miss
|