Searched refs:VectorSlavePort (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/generic/
H A DBaseTLB.py39 slave = VectorSlavePort("Port closer to the CPU side")
/gem5/src/learning_gem5/part2/
H A DSimpleCache.py40 cpu_side = VectorSlavePort("CPU side port, receives requests")
/gem5/src/mem/ruby/network/
H A DNetwork.py55 slave = VectorSlavePort("CPU slave port")
/gem5/src/gpu-compute/
H A DX86GPUTLB.py63 slave = VectorSlavePort("Port on side closer to CPU/CU")
74 slave = VectorSlavePort("Port on side closer to CPU/CU")
/gem5/src/mem/
H A DXBar.py54 slave = VectorSlavePort("Vector port for connecting masters")
/gem5/src/mem/ruby/system/
H A DSequencer.py40 slave = VectorSlavePort("CPU slave port")
/gem5/src/python/m5/
H A Dparams.py2157 VectorSlavePort = VectorResponsePort variable
2193 'VectorMasterPort', 'VectorSlavePort']

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