Searched refs:RegAddr (Results 1 - 20 of 20) sorted by relevance

/gem5/ext/nomali/lib/
H A Dmali_midgard.cc48 regs[RegAddr(L2_FEATURES)] =
54 regs[RegAddr(TILER_FEATURES)] =
59 regs[RegAddr(MEM_FEATURES)] = 0x1;
61 regs[RegAddr(MMU_FEATURES)] = 0x2830;
62 regs[RegAddr(AS_PRESENT)] = 0xff;
63 regs[RegAddr(JS_PRESENT)] = 0x7;
64 regs[RegAddr(JS0_FEATURES)] = 0x20e;
65 regs[RegAddr(JS1_FEATURES)] = 0x1fe;
66 regs[RegAddr(JS2_FEATURES)] = 0x7e;
68 regs[RegAddr(TEXTURE_FEATURES_
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H A Dregutils.hh51 getRegBlock(RegAddr addr)
63 static inline RegAddr
64 getBlockReg(RegAddr addr)
68 return RegAddr(addr.value & (BLOCK_REGS_SIZE - 1));
77 getJobSlotNo(const RegAddr &addr)
90 static inline RegAddr
91 getJobSlotAddr(const RegAddr &addr)
94 const RegAddr slot_base(RegAddr(JOB_SLOT0 + slot_no * 0x80));
109 isAddrSpaceReg(const RegAddr
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H A Dgpublock.hh63 virtual uint32_t readReg(RegAddr addr);
71 virtual void writeReg(RegAddr addr, uint32_t value);
84 virtual uint32_t readRegRaw(RegAddr addr);
97 virtual void writeRegRaw(RegAddr addr, uint32_t value);
141 const RegAddr &irq_raw_stat,
142 const RegAddr &irq_clear,
143 const RegAddr &irq_mask,
144 const RegAddr &irq_stat);
147 uint32_t readReg(RegAddr addr) override;
148 void writeReg(RegAddr add
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H A Dtypes.hh43 struct RegAddr { struct in namespace:NoMali
44 explicit RegAddr(uint32_t v) function in struct:NoMali::RegAddr
51 operator<(const RegAddr &lhs, const RegAddr &rhs) {
56 operator>(const RegAddr &lhs, const RegAddr &rhs) {
61 operator<=(const RegAddr &lhs, const RegAddr &rhs) {
66 operator>=(const RegAddr &lhs, const RegAddr
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H A Djobcontrol.hh52 uint32_t readReg(RegAddr idx) override;
53 void writeReg(RegAddr idx, uint32_t value) override;
55 uint32_t readRegRaw(RegAddr idx) override;
56 void writeRegRaw(RegAddr idx, uint32_t value) override;
H A Dmmu.hh50 uint32_t readReg(RegAddr idx) override;
51 void writeReg(RegAddr idx, uint32_t value) override;
53 uint32_t readRegRaw(RegAddr idx) override;
54 void writeRegRaw(RegAddr idx, uint32_t value) override;
H A Dmmu.cc29 RegAddr(MMU_IRQ_RAWSTAT),
30 RegAddr(MMU_IRQ_CLEAR),
31 RegAddr(MMU_IRQ_MASK),
32 RegAddr(MMU_IRQ_STATUS))
53 MMU::readReg(RegAddr addr)
63 MMU::writeReg(RegAddr addr, uint32_t value)
83 MMU::readRegRaw(RegAddr addr)
93 MMU::writeRegRaw(RegAddr addr, uint32_t value)
H A Djobcontrol.cc29 RegAddr(JOB_IRQ_RAWSTAT),
30 RegAddr(JOB_IRQ_CLEAR),
31 RegAddr(JOB_IRQ_MASK),
32 RegAddr(JOB_IRQ_STATUS))
54 JobControl::readReg(RegAddr addr)
56 if (addr >= RegAddr(JOB_SLOT0)) {
64 JobControl::writeReg(RegAddr addr, uint32_t value)
80 if (addr >= RegAddr(JOB_SLOT0))
87 JobControl::readRegRaw(RegAddr addr)
89 if (addr >= RegAddr(JOB_SLOT
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H A Dgpu.hh76 virtual uint32_t readReg(RegAddr addr);
89 virtual void writeReg(RegAddr addr, uint32_t value);
106 virtual uint32_t readRegRaw(RegAddr addr);
123 virtual void writeRegRaw(RegAddr addr, uint32_t value);
188 GPUBlock *getGPUBlock(RegAddr addr);
H A Djobslot.cc65 JobSlot::writeReg(RegAddr addr, uint32_t value)
100 return regs[RegAddr(JSn_COMMAND_NEXT)] == JSn_COMMAND_START;
107 if (regs[RegAddr(JSn_COMMAND_NEXT)] != JSn_COMMAND_START )
111 regs[RegAddr(JSn_STATUS)] = STATUS_ACTIVE.value;
115 regs.set64(RegAddr(JSn_HEAD_LO), regs.get64(RegAddr(JSn_HEAD_NEXT_LO)));
116 regs.set64(RegAddr(JSn_TAIL_LO), regs.get64(RegAddr(JSn_HEAD_NEXT_LO)));
117 regs.set64(RegAddr(JSn_AFFINITY_LO),
118 regs.get64(RegAddr(JSn_AFFINITY_NEXT_L
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H A Dgpublock.cc55 GPUBlock::readReg(RegAddr addr)
61 GPUBlock::writeReg(RegAddr addr, uint32_t value)
67 GPUBlock::readRegRaw(RegAddr addr)
73 GPUBlock::writeRegRaw(RegAddr addr, uint32_t value)
81 const RegAddr &irq_raw_stat,
82 const RegAddr &irq_clear,
83 const RegAddr &irq_mask,
84 const RegAddr &irq_stat)
96 GPUBlockInt::readReg(RegAddr addr)
106 GPUBlockInt::writeReg(RegAddr add
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H A Dgpu.cc47 GPU::readReg(RegAddr addr)
55 GPU::writeReg(RegAddr addr, uint32_t value)
64 GPU::readRegRaw(RegAddr addr)
72 GPU::writeRegRaw(RegAddr addr, uint32_t value)
101 GPU::getGPUBlock(RegAddr addr)
H A Dgpucontrol.cc42 RegAddr(GPU_IRQ_RAWSTAT),
43 RegAddr(GPU_IRQ_CLEAR),
44 RegAddr(GPU_IRQ_MASK),
45 RegAddr(GPU_IRQ_STATUS))
60 GPUControl::writeReg(RegAddr addr, uint32_t value)
82 const RegAddr ready_reg(SHADER_READY_LO +
84 const RegAddr present_reg(SHADER_PRESENT_LO +
99 const RegAddr ready_reg(SHADER_READY_LO +
H A Dmali_t7xx.cc37 regs[RegAddr(L2_FEATURES)] =
H A Dmali_t6xx.cc37 regs[RegAddr(L2_FEATURES)] =
H A Dgpucontrol.hh58 void writeReg(RegAddr idx, uint32_t value) override;
H A Djobslot.hh49 void writeReg(RegAddr idx, uint32_t value) override;
H A Daddrspace.hh49 void writeReg(RegAddr idx, uint32_t value) override;
H A Dnomali_api.cc145 *value = _gpu->readReg(NoMali::RegAddr(addr));
153 _gpu->writeReg(NoMali::RegAddr(addr), value);
165 *value = _gpu->readRegRaw(NoMali::RegAddr(addr));
173 _gpu->writeRegRaw(NoMali::RegAddr(addr), value);
H A Daddrspace.cc59 AddrSpace::writeReg(RegAddr addr, uint32_t value)

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