Searched refs:MISCREG_CR0 (Results 1 - 9 of 9) sorted by relevance

/gem5/src/arch/x86/
H A Disa.cc202 case MISCREG_CR0:
268 regVal[MISCREG_CR0],
277 regVal[MISCREG_CR0],
385 regVal[MISCREG_CR0],
408 regVal[MISCREG_CR0],
H A Dsystem.cc263 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
266 tc->setMiscReg(MISCREG_CR0, cr0);
269 tc->setMiscReg(MISCREG_CR0, cr0);
294 tc->setMiscReg(MISCREG_CR0, cr0);
H A Dfaults.cc194 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
198 tc->setMiscReg(MISCREG_CR0, newCR0);
H A Dutility.cc103 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
H A Dprocess.cc414 tc->setMiscReg(MISCREG_CR0, cr0);
631 tc->setMiscReg(MISCREG_CR0, cr0);
751 tc->setMiscReg(MISCREG_CR0, cr0);
H A Dtlb.cc392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
/gem5/src/arch/x86/regs/
H A Dmisc.hh107 MISCREG_CR0 = MISCREG_CR_BASE, enumerator in enum:X86ISA::MiscRegIndex
406 return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc840 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
1134 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc126 APPLY_SREG(cr0, MISCREG_CR0); \

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