Searched refs:MISCREG_CR0 (Results 1 - 9 of 9) sorted by relevance
/gem5/src/arch/x86/ |
H A D | isa.cc | 202 case MISCREG_CR0: 268 regVal[MISCREG_CR0], 277 regVal[MISCREG_CR0], 385 regVal[MISCREG_CR0], 408 regVal[MISCREG_CR0],
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H A D | system.cc | 263 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 266 tc->setMiscReg(MISCREG_CR0, cr0); 269 tc->setMiscReg(MISCREG_CR0, cr0); 294 tc->setMiscReg(MISCREG_CR0, cr0);
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H A D | faults.cc | 194 CR0 cr0 = tc->readMiscReg(MISCREG_CR0); 198 tc->setMiscReg(MISCREG_CR0, newCR0);
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H A D | utility.cc | 103 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
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H A D | process.cc | 414 tc->setMiscReg(MISCREG_CR0, cr0); 631 tc->setMiscReg(MISCREG_CR0, cr0); 751 tc->setMiscReg(MISCREG_CR0, cr0);
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H A D | tlb.cc | 392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
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/gem5/src/arch/x86/regs/ |
H A D | misc.hh | 107 MISCREG_CR0 = MISCREG_CR_BASE, enumerator in enum:X86ISA::MiscRegIndex 406 return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.cc | 840 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 1134 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
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/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 126 APPLY_SREG(cr0, MISCREG_CR0); \
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