Searched refs:IQ (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/cpu/o3/ |
| H A D | cpu_policy.hh | 55 * change a structure such as the IQ, simply change the typedef here
70 typedef InstructionQueue<Impl> IQ; typedef in struct:SimpleCPUPolicy
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| H A D | inst_queue_impl.hh | 54 #include "debug/IQ.hh"
141 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
153 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
185 .desc("Number of instructions added to the IQ (excludes non-spec)")
190 .desc("Number of non-speculative instructions added to the IQ")
247 .name(name() + ".IQ:residence:")
399 //Initialize thread IQ counts
405 // Initialize the number of free IQ entrie
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| H A D | iew.hh | 63 * instructions to the LSQ/IQ as part of the issue stage, and has the
64 * IQ try to issue instructions each cycle. The execute latency is
65 * actually tied into the issue latency to allow the IQ to be able to
67 * instructions. This happens by having the IQ have access to the
68 * functional units, and the IQ gets the execution latencies from the
70 * stage on the last cycle of their execution, which is when the IQ
88 typedef typename CPUPol::IQ IQ; typedef in class:DefaultIEW
147 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
212 /** Resets entries of the IQ an
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| H A D | rename.hh | 65 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
266 /** Calculates the number of free IQ entries for a specific thread. */
373 /** Count of instructions in progress that have been sent off to the IQ
378 /** Count of Load instructions in progress that have been sent off to the IQ
383 /** Count of Store instructions in progress that have been sent off to the IQ
471 * either ROB, IQ, LSQ, and it is priortized in that order.
475 IQ, enumerator in enum:DefaultRename::FullSource
504 /** Stat for total number of times that the IQ starts a stall in rename. */
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| H A D | rename_impl.hh | 142 .desc("Number of times rename has blocked due to IQ full")
580 source = IQ;
586 "[tid:%i] Blocking due to no free ROB/IQ/ entries.\n"
588 "IQ has %i free entries.\n",
603 "but only %i insts can be renamed due to ROB/IQ/LSQ limits.\n",
624 "%i insts dispatched to IQ last cycle.\n",
646 //For all kind of instructions, check ROB and IQ first
1276 DPRINTF(Rename,"[tid:%i] Stall: IQ has 0 free entries.\n", tid);
1313 DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, "
1453 case IQ
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| /gem5/src/cpu/ |
| H A D | base_dyn_inst_impl.hh | 57 #include "debug/IQ.hh"
208 DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
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