cpu/o3/iew.hh

63  * instructions to the LSQ/IQ as part of the issue stage, and has the
64  * IQ try to issue instructions each cycle. The execute latency is
65  * actually tied into the issue latency to allow the IQ to be able to
67  * instructions. This happens by having the IQ have access to the
68  * functional units, and the IQ gets the execution latencies from the
70  * stage on the last cycle of their execution, which is when the IQ
88     typedef typename CPUPol::IQ IQ;
147     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
212     /** Resets entries of the IQ and the LSQ. */
260     /** Dispatches instructions to IQ and LSQ. */
294     /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
359     IQ instQueue;
439     /** Stat for number of times the IQ becomes full. */