11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
41689SN/A * All rights reserved.
51689SN/A *
61689SN/A * Redistribution and use in source and binary forms, with or without
71689SN/A * modification, are permitted provided that the following conditions are
81689SN/A * met: redistributions of source code must retain the above copyright
91689SN/A * notice, this list of conditions and the following disclaimer;
101689SN/A * redistributions in binary form must reproduce the above copyright
111689SN/A * notice, this list of conditions and the following disclaimer in the
121689SN/A * documentation and/or other materials provided with the distribution;
131689SN/A * neither the name of the copyright holders nor the names of its
141689SN/A * contributors may be used to endorse or promote products derived from
151689SN/A * this software without specific prior written permission.
161689SN/A *
171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu *
292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
301689SN/A */
311689SN/A
322292SN/A#ifndef __CPU_O3_CPU_POLICY_HH__
332292SN/A#define __CPU_O3_CPU_POLICY_HH__
341060SN/A
358229Snate@binkert.org#include "cpu/o3/comm.hh"
368229Snate@binkert.org#include "cpu/o3/commit.hh"
378229Snate@binkert.org#include "cpu/o3/decode.hh"
388229Snate@binkert.org#include "cpu/o3/fetch.hh"
391717SN/A#include "cpu/o3/free_list.hh"
408229Snate@binkert.org#include "cpu/o3/iew.hh"
411717SN/A#include "cpu/o3/inst_queue.hh"
422292SN/A#include "cpu/o3/lsq.hh"
432292SN/A#include "cpu/o3/lsq_unit.hh"
441717SN/A#include "cpu/o3/mem_dep_unit.hh"
451717SN/A#include "cpu/o3/regfile.hh"
468229Snate@binkert.org#include "cpu/o3/rename.hh"
471717SN/A#include "cpu/o3/rename_map.hh"
481717SN/A#include "cpu/o3/rob.hh"
491717SN/A#include "cpu/o3/store_set.hh"
501061SN/A
512348SN/A/**
522348SN/A * Struct that defines the key classes to be used by the CPU.  All
532348SN/A * classes use the typedefs defined here to determine what are the
542348SN/A * classes of the other stages and communication buffers.  In order to
552348SN/A * change a structure such as the IQ, simply change the typedef here
562348SN/A * to use the desired class instead, and recompile.  In order to
572348SN/A * create a different CPU to be used simultaneously with this one, see
582348SN/A * the alpha_impl.hh file for instructions.
592348SN/A */
601060SN/Atemplate<class Impl>
611060SN/Astruct SimpleCPUPolicy
621060SN/A{
632348SN/A    /** Typedef for the freelist of registers. */
649919Ssteve.reinhardt@amd.com    typedef UnifiedFreeList FreeList;
652348SN/A    /** Typedef for the rename map. */
669919Ssteve.reinhardt@amd.com    typedef UnifiedRenameMap RenameMap;
672348SN/A    /** Typedef for the ROB. */
685553Snate@binkert.org    typedef ::ROB<Impl> ROB;
692348SN/A    /** Typedef for the instruction queue/scheduler. */
701060SN/A    typedef InstructionQueue<Impl> IQ;
712348SN/A    /** Typedef for the memory dependence unit. */
725553Snate@binkert.org    typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
732348SN/A    /** Typedef for the LSQ. */
745553Snate@binkert.org    typedef ::LSQ<Impl> LSQ;
752348SN/A    /** Typedef for the thread-specific LSQ units. */
765553Snate@binkert.org    typedef ::LSQUnit<Impl> LSQUnit;
771060SN/A
782348SN/A    /** Typedef for fetch. */
792292SN/A    typedef DefaultFetch<Impl> Fetch;
802348SN/A    /** Typedef for decode. */
812292SN/A    typedef DefaultDecode<Impl> Decode;
822348SN/A    /** Typedef for rename. */
832292SN/A    typedef DefaultRename<Impl> Rename;
842348SN/A    /** Typedef for Issue/Execute/Writeback. */
852292SN/A    typedef DefaultIEW<Impl> IEW;
862348SN/A    /** Typedef for commit. */
872292SN/A    typedef DefaultCommit<Impl> Commit;
881061SN/A
891061SN/A    /** The struct for communication between fetch and decode. */
902292SN/A    typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
911061SN/A
921061SN/A    /** The struct for communication between decode and rename. */
932292SN/A    typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
941061SN/A
951061SN/A    /** The struct for communication between rename and IEW. */
962292SN/A    typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
971061SN/A
981061SN/A    /** The struct for communication between IEW and commit. */
992292SN/A    typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
1001061SN/A
1011061SN/A    /** The struct for communication within the IEW stage. */
1025553Snate@binkert.org    typedef ::IssueStruct<Impl> IssueStruct;
1031061SN/A
1041061SN/A    /** The struct for all backwards communication. */
1052292SN/A    typedef TimeBufStruct<Impl> TimeStruct;
1061061SN/A
1071060SN/A};
1081060SN/A
1092292SN/A#endif //__CPU_O3_CPU_POLICY_HH__
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