Searched refs:CCRegClass (Results 1 - 17 of 17) sorted by relevance

/gem5/src/arch/x86/
H A Disa.hh81 case CCRegClass:
82 return RegId(CCRegClass, flattenCCIndex(regId.index()));
/gem5/src/arch/sparc/
H A Disa.hh200 case CCRegClass:
201 return RegId(CCRegClass, flattenCCIndex(regId.index()));
/gem5/src/cpu/o3/
H A Dfree_list.hh287 case CCRegClass:
320 case CCRegClass:
H A Drename_map.hh244 case CCRegClass:
288 case CCRegClass:
335 case CCRegClass:
H A Dregfile.cc124 ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
213 case CCRegClass:
H A Dthread_context.hh307 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
347 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
H A Dcpu.cc292 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
293 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
801 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
1392 RegId(CCRegClass, reg_idx));
1455 RegId(CCRegClass, reg_idx));
H A Ddyn_inst.hh238 case CCRegClass:
H A Drename_impl.hh1093 case CCRegClass:
/gem5/src/cpu/
H A Dreg_class.hh64 CCRegClass, ///< Condition-code register enumerator in enum:RegClass
164 bool isCCReg() const { return regClass == CCRegClass; }
192 case CCRegClass:
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hh70 return CCRegClass;
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.hh223 [] (RegPtr& reg) ->bool { return (reg->regClass == CCRegClass); }
H A Dtarmac_record.cc169 case CCRegClass:
/gem5/src/cpu/minor/
H A Ddyn_inst.cc174 case CCRegClass:
H A Dscoreboard.cc85 case CCRegClass:
/gem5/src/cpu/checker/
H A Dcpu_impl.hh623 case CCRegClass:
657 case CCRegClass:
/gem5/src/arch/arm/
H A Disa.hh464 case CCRegClass:
465 return RegId(CCRegClass, flattenCCIndex(regId.index()));

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