Searched refs:AddrRange (Results 1 - 25 of 107) sorted by relevance

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/gem5/src/python/pybind11/
H A Dcore.hh49 PYBIND11_MAKE_OPAQUE(std::vector<AddrRange>);
H A Dcore.cc149 py::class_<AddrRange>(m, "AddrRange")
153 .def(py::init<const std::vector<AddrRange> &>())
156 .def("__str__", &AddrRange::to_string)
158 .def("interleaved", &AddrRange::interleaved)
159 .def("granularity", &AddrRange::granularity)
160 .def("stripes", &AddrRange::stripes)
161 .def("size", &AddrRange::size)
162 .def("valid", &AddrRange::valid)
163 .def("start", &AddrRange
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/gem5/src/cpu/kvm/
H A DKvmVM.py48 VectorParam.AddrRange([], "memory ranges for coalesced MMIO")
/gem5/src/mem/
H A DAddrMapper.py69 original_ranges = VectorParam.AddrRange(
71 remapped_ranges = VectorParam.AddrRange(
H A Dphysical.hh62 BackingStoreEntry(AddrRange range, uint8_t* pmem,
71 AddrRange range;
151 void createBackingStore(AddrRange range,
254 AddrRange range, uint8_t* pmem) const;
H A DBridge.py53 ranges = VectorParam.AddrRange([AllMemory],
H A DAbstractMemory.py52 range = Param.AddrRange('128MB', "Address range (potentially interleaved)")
H A DExternalSlave.py47 addr_ranges = VectorParam.AddrRange([], 'Addresses served by'
H A Dbackdoor.hh78 const AddrRange &range() const { return _range; }
79 void range(const AddrRange &r) { _range = r; }
112 MemBackdoor(AddrRange r, uint8_t *p, Flags flags) :
117 MemBackdoor() : MemBackdoor(AddrRange(), nullptr, NoAccess)
147 AddrRange _range;
H A DSerialLink.py58 ranges = VectorParam.AddrRange([AllMemory],
H A Dphysical.cc123 vector<AddrRange> intlv_ranges;
136 AddrRange merged_range(intlv_ranges);
168 AddrRange merged_range(intlv_ranges);
185 PhysicalMemory::createBackingStore(AddrRange range,
247 vector<AddrRange> intlv_ranges;
257 ranges.push_back(AddrRange(intlv_ranges));
271 ranges.push_back(AddrRange(intlv_ranges));
327 AddrRange range, uint8_t* pmem) const
415 AddrRange range = backingStore[store_id].range;
/gem5/tests/long/se/10.mcf/
H A Dtest.py34 root.system.physmem.range=AddrRange('256MB')
/gem5/tests/quick/se/10.mcf/
H A Dtest.py34 root.system.physmem.range=AddrRange('256MB')
/gem5/src/mem/ruby/structures/
H A DDirectoryMemory.py50 addr_ranges = VectorParam.AddrRange(
/gem5/src/dev/arm/
H A Dgic_v3_distributor.hh101 static const AddrRange GICD_IGROUPR;
103 static const AddrRange GICD_ISENABLER;
105 static const AddrRange GICD_ICENABLER;
107 static const AddrRange GICD_ISPENDR;
109 static const AddrRange GICD_ICPENDR;
111 static const AddrRange GICD_ISACTIVER;
113 static const AddrRange GICD_ICACTIVER;
115 static const AddrRange GICD_IPRIORITYR;
117 static const AddrRange GICD_ITARGETSR; // GICv2 legacy
119 static const AddrRange GICD_ICFG
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H A Dgic_v2.hh82 static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
83 static const AddrRange GICD_ISENABLER; // interrupt set enable
84 static const AddrRange GICD_ICENABLER; // interrupt clear enable
85 static const AddrRange GICD_ISPENDR; // set pending interrupt
86 static const AddrRange GICD_ICPENDR; // clear pending interrupt
87 static const AddrRange GICD_ISACTIVER; // active bit registers
88 static const AddrRange GICD_ICACTIVER; // clear bit registers
89 static const AddrRange GICD_IPRIORITYR; // interrupt priority registers
90 static const AddrRange GICD_ITARGETSR; // processor target registers
91 static const AddrRange GICD_ICFG
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H A Dsmmu_v3_ports.hh93 { return AddrRangeList { AddrRange(0, UINT64_MAX) }; }
100 AddrRange addrRange;
107 AddrRange _addrRange);
/gem5/src/base/
H A Daddr_range_map.hh65 typedef std::map<AddrRange, V> RangeMap;
82 contains(const AddrRange &r) const
84 return find(r, [r](const AddrRange r1) { return r.isSubset(r1); });
87 contains(const AddrRange &r)
89 return find(r, [r](const AddrRange r1) { return r.isSubset(r1); });
124 intersects(const AddrRange &r) const
126 return find(r, [r](const AddrRange r1) { return r.intersects(r1); });
129 intersects(const AddrRange &r)
131 return find(r, [r](const AddrRange r1) { return r.intersects(r1); });
135 insert(const AddrRange
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H A Daddr_range.hh58 * The AddrRange class encapsulates an address range, and supports a
61 * AddrRange also support interleaved ranges, to stripe across cache
69 * The AddrRange is also able to coalesce a number of interleaved
72 class AddrRange class
94 AddrRange() function in class:AddrRange
126 AddrRange(Addr _start, Addr _end, const std::vector<Addr> &_masks, function in class:AddrRange
138 * Legacy constructor of AddrRange
160 AddrRange(Addr _start, Addr _end, uint8_t _intlv_high_bit, function in class:AddrRange
198 AddrRange(Addr _start, Addr _end) function in class:AddrRange
208 AddrRange(cons function in class:AddrRange
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H A Daddr_range.test.cc47 AddrRange r, r1, r2;
50 r1 = AddrRange(0x0, 0x7f);
51 r2 = AddrRange(0x80, 0xff);
53 r = AddrRange(0x0, 0xf);
57 r = AddrRange(0x80, 0x8f);
62 r1 = AddrRange(0x0, 0xff, 6, 0, 1, 0);
63 r2 = AddrRange(0x0, 0xff, 6, 0, 1, 1);
65 r = AddrRange(0x0, 0xf);
69 r = AddrRange(0x40, 0x4f);
73 r = AddrRange(
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/gem5/src/arch/arm/tracers/
H A DTarmacTrace.py65 ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0),
/gem5/src/arch/sparc/
H A DSparcSystem.py43 SimpleMemory(range=AddrRange(_rom_base, size='8MB')),
47 SimpleMemory(range=AddrRange(_nvram_base, size='8kB')),
51 SimpleMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')),
55 SimpleMemory(range=AddrRange(_partition_desc_base, size='8kB')),
/gem5/src/gpu-compute/
H A DLdsState.py45 range = Param.AddrRange('64kB', "address space of the LDS")
/gem5/src/dev/alpha/
H A Dtsunami_pchip.hh94 const AddrRange pioRange;
/gem5/src/mem/ruby/slicc_interface/
H A DController.py52 addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "

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