| /gem5/src/mem/ruby/network/simple/ |
| H A D | Switch.hh | 43 #include <vector>
65 void addInPort(const std::vector<MessageBuffer*>& in);
66 void addOutPort(const std::vector<MessageBuffer*>& out,
91 std::vector<Throttle*> m_throttles;
92 std::vector<MessageBuffer*> m_port_buffers;
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| H A D | Throttle.hh | 43 #include <vector>
63 void addLinks(const std::vector<MessageBuffer*>& in_vec,
64 const std::vector<MessageBuffer*>& out_vec);
93 std::vector<MessageBuffer*> m_in;
94 std::vector<MessageBuffer*> m_out;
96 std::vector<int> m_units_remaining;
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| /gem5/src/unittest/ |
| H A D | tokentest.cc | 33 #include <vector>
49 vector<string> tokens1;
50 vector<string> tokens2;
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| /gem5/ext/drampower/src/ |
| H A D | Parametrisable.h | 42 #include <vector>
63 * Push a new parameter into the in-order vector without checking
93 std::vector<Parameter> getParameters() const;
133 std::vector<Parameter> parameters;
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| H A D | Parametrisable.cc | 56 vector<Parameter>::iterator p = parameters.begin();
77 for (vector<Parameter>::iterator p = parameters.begin();
98 for (vector<Parameter>::const_iterator p = parameters.begin();
107 for (vector<Parameter>::const_iterator p = parameters.begin();
116 vector<Parameter> Parametrisable::getParameters() const
125 for (vector<Parameter>::const_iterator p = parameters.begin();
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| /gem5/ext/dsent/model/optical_graph/ |
| H A D | OpticalNode.h | 34 typedef std::vector<DetectorEntry> DetectorTable;
62 vector<OpticalNode*>* getDownstreamNodes() const;
101 vector<OpticalNode*>* m_downstream_nodes_;
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| /gem5/src/arch/x86/bios/ |
| H A D | acpi.hh | 44 #include <vector>
108 std::vector<SysDescTable *> entries;
119 std::vector<SysDescTable *> entries;
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| H A D | e820.hh | 43 #include <vector>
71 std::vector<E820Entry *> entries;
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| /gem5/src/sim/ |
| H A D | voltage_domain.hh | 44 #include <vector>
135 typedef std::vector<double> Voltages;
155 typedef std::vector<SrcClockDomain *> SrcClockChildren;
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| /gem5/src/gpu-compute/ |
| H A D | hsa_code.hh | 40 #include <vector>
78 std::vector<TheGpuISA::RawMachInst>* insts() { return &_insts; }
95 std::vector<TheGpuISA::RawMachInst> _insts;
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| H A D | hsa_object.hh | 41 #include <vector>
57 static std::vector<std::function<HsaObject*(const std::string&, int,
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| /gem5/src/cpu/ |
| H A D | intr_control.cc | 35 #include <vector>
53 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
62 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
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| /gem5/src/mem/ruby/network/fault_model/ |
| H A D | FaultModel.hh | 136 std::vector <system_conf> configurations;
137 std::vector <system_conf> routers;
138 std::vector <int> temperature_weights;
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| /gem5/src/mem/ruby/network/garnet2.0/ |
| H A D | NetworkLink.hh | 38 #include <vector>
64 const std::vector<unsigned int> & getVcLoad() const { return m_vc_load; }
86 std::vector<unsigned int> m_vc_load;
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| /gem5/tests/test-progs/pthread/src/ |
| H A D | test_std_thread.cpp | 42 #include <vector>
57 std::vector< std::thread > threads;
58 std::vector<int> outputs( MAX_N_WORKER_THREADS, 0 );
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | stream_gen.hh | 57 // A non empty vector of StreamIDs must be provided.
59 // vector means that they are not used and no configuration
62 "Must provide a vector of StreamIDs");
100 std::vector<uint32_t> streamIds;
101 std::vector<uint32_t> substreamIds;
138 uint32_t randomPick(const std::vector<uint32_t> &svec);
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_tracer.hh | 125 std::vector<InstPtr> instQueue;
126 std::vector<MemPtr> memQueue;
127 std::vector<RegPtr> regQueue;
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| /gem5/src/arch/x86/ |
| H A D | interrupts.hh | 82 Bitfield<7, 0> vector; member in class:X86ISA::Interrupts
151 setRegArrayBit(ApicRegIndex base, uint8_t vector) argument
153 regs[base + (vector / 32)] |= (1 << (vector % 32));
157 clearRegArrayBit(ApicRegIndex base, uint8_t vector) argument
159 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
163 getRegArrayBit(ApicRegIndex base, uint8_t vector) argument
165 return bits(regs[base + (vector / 32)], vector
[all...] |
| /gem5/ext/systemc/src/sysc/kernel/ |
| H A D | sc_spawn_options.h | 35 #include <vector>
108 std::vector<sc_spawn_reset_base*> m_resets;
109 std::vector<const sc_event*> m_sensitive_events;
110 std::vector<sc_event_finder*> m_sensitive_event_finders;
111 std::vector<sc_interface*> m_sensitive_interfaces;
112 std::vector<sc_port_base*> m_sensitive_port_bases;
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| /gem5/src/arch/mips/ |
| H A D | isa.hh | 36 #include <vector>
71 std::vector<std::vector<RegVal> > miscRegFile;
72 std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
73 std::vector<BankType> bankType;
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| /gem5/src/cpu/pred/ |
| H A D | ras.hh | 34 #include <vector>
90 std::vector<TheISA::PCState> addrStack;
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| /gem5/src/mem/probes/ |
| H A D | base.hh | 44 #include <vector>
93 std::vector<std::unique_ptr<PacketListener>> listeners;
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| /gem5/src/mem/ruby/structures/ |
| H A D | BankedArray.hh | 35 #include <vector>
61 std::vector<AccessRecord> busyBanks;
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| /gem5/ext/nomali/lib/ |
| H A D | jobcontrol.hh | 23 #include <vector>
90 std::vector<JobSlot> slots;
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| H A D | mmu.hh | 23 #include <vector>
60 std::vector<AddrSpace> spaces;
|