Searched refs:vector (Results 426 - 450 of 763) sorted by relevance

<<11121314151617181920>>

/gem5/src/cpu/checker/
H A Dcpu.cc146 const std::vector<bool>& byte_enable,
165 mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
179 const std::vector<bool>& byteEnable)
261 const std::vector<bool>& byteEnable)
/gem5/src/cpu/
H A Dthread_context.cc81 // Then loop through the vector registers.
177 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
183 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
218 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
224 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
H A Dtimebuf.hh37 #include <vector>
49 std::vector<char *> index;
/gem5/src/python/pybind11/
H A Ddebug.cc49 #include <vector>
/gem5/src/arch/arm/
H A Dremote_gdb.hh122 std::vector<std::string>
/gem5/src/base/stats/
H A Dgroup.cc124 const std::vector<Info *> &
/gem5/src/dev/x86/
H A Di8254.hh66 std::vector<IntSourcePin<I8254> *> intPin;
H A Dcmos.hh59 std::vector<IntSourcePin<X86RTC> *> intPin;
/gem5/src/cpu/simple/
H A Dtiming.hh287 const std::vector<bool>& byteEnable =std::vector<bool>())
292 const std::vector<bool>& byteEnable = std::vector<bool>())
H A Dexec_context.hh93 // Number of vector alu accesses
108 // Number of vector instructions
119 // Number of vector register file accesses
218 /** Reads a vector register. */
228 /** Reads a vector register for modification. */
238 /** Sets a vector register to a value. */
251 /** Reads source vector lane. */
261 /** Reads source vector 8bit operand. */
267 /** Reads source vector 16bit operand. */
273 /** Reads source vector 3
[all...]
/gem5/ext/dsent/model/
H A DModel.cc24 #include <vector>
30 using std::vector;
78 m_property_names_ = new vector<String>;
79 m_parameter_names_ = new vector<String>;
163 const vector<String>* Model::getParameterNames() const
185 const vector<String>* Model::getPropertyNames() const
433 vector<String> hier_split = query_hier_.splitByString(HIERARCHY_SEPARATOR);
/gem5/src/mem/
H A Ddram_ctrl.hh60 #include <vector>
274 * Rank class includes a vector of banks. Refresh and Power state
428 std::vector<Command> cmdList;
434 std::vector<Bank> banks;
880 std::pair<std::vector<uint32_t>, bool>
927 std::vector<DRAMPacketQueue> readQueue;
928 std::vector<DRAMPacketQueue> writeQueue;
952 std::vector<Rank*> ranks;
/gem5/src/cpu/minor/
H A Dlsq.hh192 * non-faulting vector loads).*/
409 std::vector<RequestPtr> fragmentRequests;
412 std::vector<Packet *> fragmentPackets;
535 std::vector<InstSeqNum> lastMemBarrier;
712 const std::vector<bool>& byteEnable =
713 std::vector<bool>());
H A Dfunc_unit.cc158 const std::vector<unsigned> &cant_forward =
161 /* Setup the bit vector cantForward... with the set indices
213 const std::vector<MinorFUTiming *> &timings =
/gem5/src/systemc/ext/utils/
H A Dsc_vector.hh56 #include <vector>
174 const std::vector<sc_object *> &get_elements() const;
177 std::vector<void *> objs;
181 mutable std::vector<sc_object *> elements;
291 typedef std::vector<void *> StorageType;
296 typedef typename std::vector<void *>::iterator type;
301 typedef typename std::vector<void *>::const_iterator type;
449 sc_vector() : sc_vector_base(::sc_core::sc_gen_unique_name("vector")) {}
653 std::vector<sc_object *>
656 std::vector<sc_objec
[all...]
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_thread_process.cpp177 const std::vector<sc_object*>& children = get_child_objects();
235 const std::vector<sc_object*>& children = get_child_objects();
280 const std::vector<sc_object*> children = get_child_objects();
353 const std::vector<sc_object*>& children = get_child_objects();
510 const std::vector<sc_object*>& children = get_child_objects();
637 const std::vector<sc_object*> children = get_child_objects();
H A Dsc_simcontext_int.h160 std::vector<sc_thread_handle>* invokers_p; // active invokers stack.
284 std::vector<sc_thread_handle>&
/gem5/src/cpu/o3/
H A Dcpu.hh54 #include <vector>
320 /** Check if a change in renaming is needed for vector registers.
362 * Read physical vector register for modification.
366 /** Returns current vector renaming mode */
369 /** Sets the current vector renaming mode */
374 * Read physical vector register lane
385 * Read physical vector register lane
395 /** Write a lane of the destination vector register. */
429 /** Read architectural vector register for modification. */
432 /** Read architectural vector registe
[all...]
/gem5/ext/pybind11/tests/
H A Dtest_sequences_and_iterators.cpp102 Sequence(const std::vector<float> &value) : m_size(value.size()) {
103 print_created(this, "of size", m_size, "from std::vector");
180 .def(py::init<const std::vector<float>&>())
261 IntPairs(std::vector<std::pair<int, int>> data) : data_(std::move(data)) {}
264 std::vector<std::pair<int, int>> data_;
267 .def(py::init<std::vector<std::pair<int, int>>>())
350 static std::vector<int> list = { 1, 2, 3 };
/gem5/ext/dsent/
H A Dinterface.cc140 vector<unsigned int> num_vchannels_vec(num_vclass, num_vchannels);
141 vector<unsigned int> num_buffers_vec(num_vclass, num_buffers);
/gem5/ext/dsent/model/optical_graph/
H A DOpticalGraph.cc77 const vector<OpticalDataPath>* data_paths = wavelength->getDataPaths();
191 vector<OpticalNode*>* d_nodes = node_->getDownstreamNodes();
/gem5/ext/dsent/model/std_cells/
H A DStdCellLib.cc128 const vector<String>& cell_sizes = getTechModel()->get("StdCell->AvailableSizes").split("[,]");
183 const String StdCellLib::genDrivingStrengthString(const vector<double>& driving_strength_) const
/gem5/src/mem/ruby/network/simple/
H A DThrottle.cc70 Throttle::addLinks(const vector<MessageBuffer*>& in_vec,
71 const vector<MessageBuffer*>& out_vec)
H A DSimpleNetwork.cc52 for (vector<BasicRouter*>::const_iterator i = p->routers.begin();
113 std::vector<MessageBuffer*> queues(m_virtual_networks);
/gem5/src/systemc/ext/core/
H A Dsc_event.hh36 #include <vector>
248 const std::vector<sc_event *> &sc_get_top_level_events();

Completed in 52 milliseconds

<<11121314151617181920>>