Searched refs:vaddr (Results 51 - 72 of 72) sorted by relevance

123

/gem5/src/gpu-compute/
H A Dcompute_unit.cc777 Addr vaddr = pkt->req->getVaddr(); local
780 if ((vaddr + size - 1) % 64 < vaddr % 64) {
782 cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr);
787 if (!p->pTable->translate(vaddr, paddr)) {
788 if (!p->fixupStackFault(vaddr)) {
791 vaddr);
1092 DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId,
1115 Addr vaddr = pkt->req->getVaddr(); local
1153 int stride = last ? (roundDown(vaddr, TheIS
[all...]
H A Dtlb_coalescer.cc154 Addr first_entry_vaddr = tlb_entry->vaddr;
/gem5/util/minorview/
H A Dmodel.py479 def __init__(self, id, vaddr, paddr, size, pairs={}):
481 self.vaddr = vaddr
486 ret = ["0x%x/0x%x" % (self.vaddr, self.paddr), "%d" % self.size]
493 def __init__(self, id, fault, vaddr, pairs={}):
495 self.vaddr = vaddr
499 ret = ["0x%x" % self.vaddr, self.fault]
706 vaddr = int(pairs['vaddr'],
[all...]
/gem5/src/cpu/
H A Dsimple_thread.hh169 void demapPage(Addr vaddr, uint64_t asn) argument
171 itb->demapPage(vaddr, asn);
172 dtb->demapPage(vaddr, asn);
175 void demapInstPage(Addr vaddr, uint64_t asn) argument
177 itb->demapPage(vaddr, asn);
180 void demapDataPage(Addr vaddr, uint64_t asn) argument
182 dtb->demapPage(vaddr, asn);
H A Dbase_dyn_inst.hh293 void demapPage(Addr vaddr, uint64_t asn) argument
295 cpu->demapPage(vaddr, asn);
297 void demapInstPage(Addr vaddr, uint64_t asn) argument
299 cpu->demapPage(vaddr, asn);
301 void demapDataPage(Addr vaddr, uint64_t asn) argument
303 cpu->demapPage(vaddr, asn);
H A Dexec_context.hh336 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
/gem5/src/cpu/checker/
H A Dcpu.hh510 demapPage(Addr vaddr, uint64_t asn) override
512 this->itb->demapPage(vaddr, asn);
513 this->dtb->demapPage(vaddr, asn);
525 demapInstPage(Addr vaddr, uint64_t asn) argument
527 this->itb->demapPage(vaddr, asn);
531 demapDataPage(Addr vaddr, uint64_t asn) argument
533 this->dtb->demapPage(vaddr, asn);
/gem5/src/arch/arm/
H A Dtable_walker.cc133 vaddr(0), vaddr_tainted(0),
262 currState->vaddr = purifyTaggedAddr(currState->vaddr_tainted,
265 currState->vaddr = currState->vaddr_tainted;
372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
438 te = tlb->lookup(currState->vaddr, currState->asid,
463 currState->vaddr_tainted, currState->ttbcr, mbits(currState->vaddr, 31,
468 if (currState->ttbcr.n == 0 || !mbits(currState->vaddr, 31,
513 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
603 if (currState->vaddr <= ttbr0_max) {
627 } else if (currState->vaddr >
[all...]
H A Dtlb.hh232 void insert(Addr vaddr, TlbEntry &pte);
311 void demapPage(Addr vaddr, uint64_t asn) override
321 * @param vaddr virtual address to translate
325 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
H A Dtable_walker.hh721 Addr vaddr; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
/gem5/src/sim/
H A Dpseudo_inst.cc491 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) argument
494 vaddr, len, offset);
527 tc->getVirtProxy().writeBlob(vaddr, buf, result);
533 writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, argument
537 vaddr, len, offset, filename_addr);
563 tc->getVirtProxy().readBlob(vaddr, buf, len);
/gem5/src/mem/
H A Drequest.hh268 /** Whether or not the vaddr & asid are valid. */
317 * The size of the request. This field must be set when vaddr or
342 * latencies. This field is set to curTick() any time paddr or vaddr
459 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument
467 setVirt(asid, vaddr, size, flags, mid, pc);
471 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument
475 setVirt(asid, vaddr, size, flags, mid, pc, std::move(atomic_op));
529 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument
533 _vaddr = vaddr;
702 /** Accessor function for vaddr
[all...]
/gem5/src/arch/sparc/
H A Dfaults.cc633 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
634 panic_if(!pte, "Tried to execute unmapped address %#x.\n", vaddr);
636 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
688 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
689 if (!pte && p->fixupStackFault(vaddr))
690 pte = p->pTable->lookup(vaddr);
691 panic_if(!pte, "Tried to access unmapped address %#x.\n", vaddr);
693 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
H A Dtlb.hh164 demapPage(Addr vaddr, uint64_t asn) override
/gem5/src/arch/x86/
H A Dpagetable_walker.hh139 void setupWalk(Addr vaddr);
/gem5/src/dev/net/
H A Dsinic.cc369 Addr vaddr = Regs::get_RxData_Addr(reg64); local
370 Addr paddr = vtophys(req->xc, vaddr);
372 "vaddr=%#x, paddr=%#x\n",
373 index, vnic.rxUnique, vaddr, paddr);
407 Addr vaddr = Regs::get_TxData_Addr(reg64); local
408 Addr paddr = vtophys(req->xc, vaddr);
410 "vaddr=%#x, paddr=%#x\n",
411 index, vnic.txUnique, vaddr, paddr);
/gem5/src/cpu/simple/
H A Dexec_context.hh543 demapPage(Addr vaddr, uint64_t asn) override
545 thread->demapPage(vaddr, asn);
/gem5/src/arch/mips/
H A Dpra_constants.hh277 Bitfield<63, 3> vaddr; member in namespace:MipsISA
/gem5/src/arch/riscv/
H A Dpra_constants.hh277 Bitfield<63, 3> vaddr; member in namespace:RiscvISA
/gem5/src/cpu/o3/
H A Dfetch.hh312 * @param vaddr The memory address that is being fetched from.
319 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
H A Dlsq.hh460 setVirt(int asid, Addr vaddr, unsigned size, Request::Flags flags_, argument
463 request()->setVirt(asid, vaddr, size, flags_, mid, pc);
H A Dfetch_impl.hh604 DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) argument
627 Addr fetchBufferBlockPC = fetchBufferAlignPC(vaddr);
630 tid, fetchBufferBlockPC, vaddr);

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