| /gem5/src/mem/ruby/profiler/ |
| H A D | AccessTraceForAddress.hh | 51 void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
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| H A D | AddressProfiler.cc | 296 update(type, access_mode, id, sharing_miss);
303 update(type, access_mode, id, sharing_miss);
307 update(type, access_mode, id, sharing_miss);
315 update(type, access_mode, id, sharing_miss);
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| /gem5/ext/testlib/ |
| H A D | helper.py | 201 def update(self, keys): member in class:OrderedSet
273 self.update(dict_)
290 def update(self, items): member in class:AttrDict
291 self.__dict__.update(items)
308 def update(self, items): member in class:FrozenAttrDict
313 super(FrozenAttrDict, self).update(items)
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| /gem5/ext/dsent/model/electrical/router/ |
| H A D | Router.cc | 201 getSubInstance("PipelineReg0")->update();
202 getSubInstance("InputPort")->update();
203 getSubInstance("PipelineReg1")->update();
204 getSubInstance("Crossbar_Sel_DFF")->update();
205 getSubInstance("Crossbar")->update();
208 getSubInstance("PipelineReg2_" + (String)i)->update();
210 getSubInstance("SwitchAllocator")->update();
218 clock_tree->update();
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| /gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/ |
| H A D | tlm_fifo.h | 153 void update();
205 // init and update
238 tlm_fifo<T>::update() function in class:tlm::tlm_fifo
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| /gem5/src/systemc/core/ |
| H A D | process.hh | 223 update();
228 void update() { _process->signalReset(_signal->read() == _value, _sync); } function in class:sc_gem5::Reset
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record.hh | 124 * This updates the register entry using the update table. It is
127 * The entry update cannot be done automatically at TraceRegEntry
132 void update(const TarmacContext& tarmCtx);
139 /** Register update functions. */
205 /** Generate and update a register entry. */
211 single_reg.update(tarmCtx);
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| /gem5/util/statetrace/arch/sparc/ |
| H A D | tracechild.hh | 87 bool update(int pid);
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| /gem5/src/cpu/pred/ |
| H A D | btb.cc | 130 DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
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| H A D | tage.cc | 56 TAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history, function in class:TAGE
67 // This restores the global history, then update it
82 // optional non speculative update of the histories
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| H A D | ltage.cc | 94 LTAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history, function in class:LTAGE
105 // This restores the global history, then update it
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| /gem5/src/python/m5/util/ |
| H A D | attrdict.py | 54 self.update(state)
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| H A D | sorteddict.py | 141 def update(self, *args, **kwargs): member in class:SortedDict
142 dict.update(self, *args, **kwargs)
201 d.update({'b' : 2, 'h' : 8})
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| H A D | jobfile.py | 38 self.__dict__.update(kwargs)
40 def update(self, obj): member in class:Data
42 raise AttributeError("can only update from Data object")
142 self.update(self._config)
144 self.update(group)
149 self.update(option)
154 self.update(option._suboption)
236 option.update(self)
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| /gem5/src/mem/cache/prefetch/ |
| H A D | spatio_temporal_memory_streaming.hh | 111 void update(ActiveGenerationTableEntry const &e) function in struct:STeMSPrefetcher::ActiveGenerationTableEntry
124 // Search for the offset in the deltas array, if it exist, update
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| /gem5/ext/dsent/model/optical/ |
| H A D | SWMRLink.cc | 137 laser->update();
143 modulator->update();
149 detector->update();
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| /gem5/util/batch/ |
| H A D | send.py | 117 update = True variable
138 update = False variable
159 if update and not listonly and not onlyecho and isdir(conf.linkdir):
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| /gem5/util/pbs/ |
| H A D | send.py | 118 update = True variable
139 update = False variable
160 if update and not listonly and not onlyecho and isdir(conf.linkdir):
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| /gem5/ext/systemc/src/sysc/communication/ |
| H A D | sc_signal.h | 187 virtual void update();
258 sc_signal<T,POL>::update() function in class:sc_core::sc_signal
260 policy_type::update();
416 virtual void update();
582 virtual void update();
659 // Andy Goodrich: Copyright update.
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| /gem5/ext/dsent/model/network/ |
| H A D | ElectricalClos.cc | 416 input_to_ingress_link->update();
422 ingress_to_middle_link->update();
428 middle_to_egress_link->update();
434 egress_to_output_link->update();
437 ingress_router->update();
443 middle_router->update();
449 egress_router->update();
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| H A D | PhotonicClos.cc | 438 input_to_ingress_link->update();
443 ingress_to_middle_link->update();
448 middle_to_egress_link->update();
454 egress_to_output_link->update();
457 ingress_router->update();
462 middle_router->update();
467 egress_router->update();
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| H A D | ElectricalMesh.cc | 276 rr_link->update();
282 rs_link->update();
285 router->update();
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| /gem5/src/systemc/ext/channel/ |
| H A D | sc_signal.hh | 303 update() function in class:sc_core::sc_signal
357 update() function in class:sc_core::sc_signal
423 update() function in class:sc_core::sc_signal
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| /gem5/util/statetrace/arch/amd64/ |
| H A D | tracechild.hh | 102 bool update(int pid);
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| /gem5/src/mem/ |
| H A D | dramsim2_wrapper.cc | 199 dramsim->update();
|