/gem5/src/sim/ |
H A D | process.cc | 55 #include <map> 178 for (auto map : mappings) { 179 Addr paddr, vaddr = map.first; 300 pTable->map(vaddr, paddr, size, 319 pTable->map(vaddr, new_paddr, PageBytes, clobber); 384 Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) function in class:Process 386 pTable->map(vaddr, paddr, size,
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H A D | process.hh | 39 #include <map> 147 * This function exists primarily to expose the map operation to 154 * @return True if the map operation was successful. (At this 155 * point in time, the map operation always succeeds.) 157 bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true);
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H A D | eventq.cc | 321 std::unordered_map<long, bool> map; local 341 if (map[reinterpret_cast<long>(nextInBin)]) { 346 map[reinterpret_cast<long>(nextInBin)] = true;
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/gem5/ext/pybind11/tests/ |
H A D | test_stl.cpp | 81 m.def("cast_map", []() { return std::map<std::string, std::string>{{"key", "value"}}; }); 82 m.def("load_map", [](const std::map<std::string, std::string> &map) { 83 return map.at("key") == "value" && map.at("key2") == "value2"; 95 // NB: map and set keys are `const`, so while we technically do move them (as `const Type &&`), 102 v.back()[0].emplace_back(); // add a map to the array 105 v.back()[1].emplace_back(); // add a map to the array
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/gem5/src/dev/virtio/ |
H A D | fs9p.hh | 43 #include <map> 201 std::map<P9Tag, VirtDescriptor *> pendingTransactions;
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/sc_process_handle_less_than/ |
H A D | sc_process_handle_less_than.cpp | 36 #include <map> 68 std::map<sc_process_handle, int> m;
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/gem5/src/systemc/utils/ |
H A D | vcd.hh | 33 #include <map> 46 std::map<std::string, VcdTraceScope *> scopes;
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/gem5/src/systemc/tlm_utils/ |
H A D | instance_specific_extensions.cc | 23 #include <map> 42 typedef std::map<std::type_index, key_type> type_map;
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/gem5/src/systemc/tests/ |
H A D | verify.py | 188 map(run_test, runnable) 191 map(lambda t: tp.apply_async(run_test, (t,)), runnable) 244 filts = map(lambda f: '(' + f + ')', filts) 303 bases = map(lambda t: t[:-len(platform)], suffixed) 366 total_failed = sum(map(len, self._failed.values())) 373 'passed': map(lambda t: t.props, self._passed), 375 cause: map(lambda t: t.props, tests) for 480 tags = map(lambda d: d.tag, failed_diffs)
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/gem5/src/base/ |
H A D | addr_range_map.hh | 50 #include <map> 57 * The AddrRangeMap uses an STL map to implement an interval tree for 65 typedef std::map<AddrRange, V> RangeMap; 74 * Searches through the ranges in the address map and returns an 95 * Searches through the ranges in the address map and returns an 116 * Searches through the ranges in the address map and returns an 204 * Add an address range map entry to the cache. 206 * @param it Iterator to the entry in the address range map 231 * Searches through the ranges in the address map and returns an 286 * recently used entries in the address range map [all...] |
H A D | cp_annotate.hh | 47 #include <map> 251 typedef std::map<System*, std::pair<std::string, int> > NameCache; 255 typedef std::map<StackId, std::vector<int> > SmStack; 257 // map of each context and if it's currently in explict state mode 259 typedef std::map<StackId, bool> SwExpl; 261 typedef std::map<int,int> IMap; 266 typedef std::map<int, int> LinkMap; 361 // might need to put smstackid into map here, but perhaps not 410 std::map<std::string, SymbolTable*> userApp;
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.hh | 192 std::map<Addr, MessageBuffer*> m_block_map; 196 typedef std::map<Addr, MsgVecType* > WaitingBufType;
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/gem5/src/mem/ruby/system/ |
H A D | RubySystem.hh | 140 std::vector<std::map<uint32_t, AbstractController *> > m_abstract_controls;
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/gem5/src/gpu-compute/ |
H A D | hsail_code.hh | 41 #include <map> 207 std::map<std::string, Label> map; member in class:LabelMap 240 typedef std::map<const Brig::BrigDirectiveVariable*, StorageElement*>
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/gem5/src/systemc/ext/channel/ |
H A D | sc_signal_rv.hh | 136 std::map<::sc_gem5::Process *, sc_dt::sc_lv<W> > inputs;
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/gem5/src/arch/mips/ |
H A D | tlb.hh | 38 #include <map>
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/gem5/src/arch/riscv/ |
H A D | tlb.hh | 38 #include <map>
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/gem5/tests/test-progs/asmtest/src/riscv/ |
H A D | run-tests.py | 122 job_outputs = job_pool.map(subprocess.call, job_cmds)
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/gem5/util/plot_dram/ |
H A D | dram_lat_mem_rd_plot.py | 117 final_rd_lat = map(lambda p: min(p), zip(*rd_lat))
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/gem5/src/mem/ |
H A D | page_table.hh | 118 virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0);
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/gem5/src/mem/ruby/network/ |
H A D | Topology.hh | 64 typedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap;
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/gem5/ext/systemc/src/tlm_utils/ |
H A D | multi_passthrough_target_socket.h | 255 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES>*>& multi_binds=get_hierarch_bind()->get_multi_binds(); 307 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES>*>& get_multi_binds(){return m_multi_binds;} 314 //map that stores to which index a multi init socket is connected 316 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES>*> m_multi_binds;
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/gem5/src/cpu/o3/ |
H A D | inst_queue.hh | 48 #include <map> 69 * Similar to the rename map and the free list, it expects that 363 std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 365 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 449 * the scoreboard that exists in the rename map.
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/gem5/src/systemc/ext/tlm_utils/ |
H A D | multi_passthrough_target_socket.h | 239 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES> *> & 321 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES> *> & 336 std::map<unsigned int, tlm::tlm_bw_transport_if<TYPES> *> m_multi_binds;
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/gem5/src/systemc/core/ |
H A D | scheduler.hh | 34 #include <map> 162 typedef std::map<Tick, TimeSlot *> TimeSlots; 490 std::map<::Event *, Tick> eventsToSchedule;
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