1/*
2 * Copyright 2018 Google, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Gabe Black
28 */
29
30#ifndef __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__
31#define __SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__
32
33#include "../core/sc_module.hh" // for sc_gen_unique_name
34#include "../dt/bit/sc_logic.hh"
35#include "../dt/bit/sc_lv.hh"
36#include "sc_signal.hh"
37
38namespace sc_gem5
39{
40
41class Process;
42Process *getCurrentProcess();
43
44} // namespace sc_gem5
45
46namespace sc_dt
47{
48
49template <int W>
50class sc_lv;
51
52};
53
54namespace sc_core
55{
56
57class sc_port_base;
58
59template <int W>
60class sc_signal_rv : public sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>
61{
62  public:
63    sc_signal_rv() : sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>(
64            sc_gen_unique_name("signal_rv"))
65    {}
66    sc_signal_rv(const char *name) :
67            sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>(name)
68    {}
69    virtual ~sc_signal_rv() {}
70
71    virtual void register_port(sc_port_base &, const char *) {}
72
73    virtual void
74    write(const sc_dt::sc_lv<W> &l)
75    {
76        ::sc_gem5::Process *p = ::sc_gem5::getCurrentProcess();
77
78        auto it = inputs.find(p);
79        if (it == inputs.end()) {
80            inputs.emplace(p, l);
81            this->request_update();
82        } else if (it->second != l) {
83            it->second = l;
84            this->request_update();
85        }
86    }
87    sc_signal_rv<W> &
88    operator = (const sc_dt::sc_lv<W> &l)
89    {
90        write(l);
91        return *this;
92    }
93    sc_signal_rv<W> &
94    operator = (const sc_signal_rv<W> &r)
95    {
96        write(r.read());
97        return *this;
98    }
99
100    virtual const char *kind() const { return "sc_signal_rv"; }
101
102  protected:
103    virtual void
104    update()
105    {
106        using sc_dt::Log_0;
107        using sc_dt::Log_1;
108        using sc_dt::Log_Z;
109        using sc_dt::Log_X;
110        static sc_dt::sc_logic_value_t merge_table[4][4] = {
111            { Log_0, Log_X, Log_0, Log_X },
112            { Log_X, Log_1, Log_1, Log_X },
113            { Log_0, Log_1, Log_Z, Log_X },
114            { Log_X, Log_X, Log_X, Log_X }
115        };
116
117        // Resolve the inputs, and give the result to the underlying
118        // signal class.
119        for (int i = 0; i < W; i++) {
120            sc_dt::sc_logic_value_t bit = Log_Z;
121            for (auto &input: inputs)
122                bit = merge_table[bit][input.second.get_bit(i)];
123            this->m_new_val.set_bit(i, bit);
124        }
125
126        // Ask the signal to update it's value.
127        sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>::update();
128    }
129
130  private:
131    // Disabled
132    sc_signal_rv(const sc_signal_rv<W> &) :
133            sc_signal<sc_dt::sc_lv<W>, SC_MANY_WRITERS>()
134    {}
135
136    std::map<::sc_gem5::Process *, sc_dt::sc_lv<W> > inputs;
137};
138
139} // namespace sc_core
140
141#endif  //__SYSTEMC_EXT_CHANNEL_SC_SIGNAL_RV_HH__
142