Searched refs:fatal (Results 126 - 150 of 220) sorted by relevance

123456789

/gem5/src/arch/power/
H A Dtlb.cc186 fatal("TLB Insert not yet implemented\n");
316 fatal("translate atomic not yet implemented in full system mode.\n");
/gem5/src/dev/arm/
H A Drv_ctrl.cc230 fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d "
245 fatal("Oscillator frequency out of range: %f\n",
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py45 from m5.util import fatal, panic
53 fatal("This system assumes MSI from learning gem5!")
H A Druby_caches_MI_example.py47 from m5.util import fatal, panic
55 fatal("This system assumes MI_example!")
/gem5/src/gpu-compute/
H A Dlds_state.cc249 fatal("not implemented");
270 fatal("not implemented");
H A Dbrig_object.cc159 fatal("Bad directive size 0\n");
426 fatal("%s: BRIG version mismatch, %d.%d != %d.%d\n",
/gem5/src/cpu/minor/
H A Ddecode.cc65 fatal("%s: executeInputWidth must be >= 1 (%d)\n", name, outputWidth);
68 fatal("%s: decodeInputBufferSize must be >= 1 (%d)\n", name,
H A Dexecute.cc96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_,
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
366 fatal("Received error response packet for inst: %s\n", *inst);
394 fatal("There should only ever be reads, "
/gem5/src/mem/
H A Ddramsim2.cc84 fatal("DRAMSim2 %s is unconnected!\n", name());
90 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
H A Dmem_delay.cc59 fatal("Memory delay is not connected on both sides.\n");
H A Ddram_ctrl.cc120 fatal("Write buffer low threshold %d must be smaller than the "
147 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
155 fatal("banks per rank (%d) must be equal to or larger than "
161 fatal("Banks per rank (%d) must be evenly divisible by bank groups "
167 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
173 fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when "
180 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
194 fatal("DRAMCtrl %s is unconnected!\n", name());
203 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
208 fatal("Channe
[all...]
/gem5/src/python/m5/
H A Dsimulate.py61 from .util import fatal
83 fatal("Need to instantiate Root() before calling instantiate()")
/gem5/src/arch/hsail/insts/
H A Dmem_impl.hh116 fatal("Bad ld register dest operand, num vector operands: %d \n",
339 fatal("Load to unsupported segment %d %llxe\n", this->segment,
495 fatal("Store to unsupported segment %d\n", this->segment);
535 default: fatal("Bad ld register src operand, num vector operands: "
612 fatal("Atomic op to unsupported segment %d\n",
/gem5/src/base/
H A Dstatistics.cc555 fatal("Stats are already enabled");
566 fatal("No registered Stats::dump handler");
575 fatal("No registered Stats::reset handler");
/gem5/src/arch/hsail/
H A Doperand.hh544 fatal("RegOrImmOperand::init(): bad operand kind %d\n",
565 fatal("RegOrImmOperand::init(): bad operand kind %d\n",
655 fatal("RegAddrOperand: bad operand kind %d\n", baseOp->kind);
664 fatal("can't do calcUniform() on register-based address\n");
/gem5/src/mem/ruby/system/
H A DCacheRecorder.cc182 fatal("Unable to allocate buffer of size %s\n",
/gem5/src/mem/ruby/network/garnet2.0/
H A DRoutingUnit.cc105 fatal("Fatal Error:: No Route exists from this Router.");
/gem5/src/python/m5/util/
H A D__init__.py64 # fatal() should be called when the simulation cannot continue due to
67 def fatal(fmt, *args): function
68 print('fatal:', fmt % args, file=sys.stderr)
/gem5/src/mem/ruby/network/
H A DMessageBuffer.hh85 fatal("Trying to connect %s to MessageBuffer %s. \
/gem5/src/cpu/kvm/
H A Dvm.cc71 fatal("KVM: Failed to open /dev/kvm\n");
75 fatal("KVM: Incompatible API version\n");
/gem5/src/arch/x86/
H A Dsystem.cc112 fatal("No kernel to load.\n");
115 fatal("Loading a 32 bit x86 kernel is not supported.\n");
/gem5/src/mem/cache/tags/
H A Dfa_lru.cc73 fatal("cache block size (in bytes) `%d' must be a power of two",
76 fatal("Cache Size must be power of 2 for now");
/gem5/src/systemc/core/
H A Dscheduler.cc374 fatal("Pausing systemc after sc_main completed.");
394 fatal("Stopping systemc after sc_main completed.");
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.cc109 fatal("The port of %s is not connected!\n", name());
331 fatal("BaseTrafficGen %s spent %llu ticks without making progress",
/gem5/configs/common/
H A DFSConfig.py277 fatal("The currently selected ARM platforms doesn't support" \
324 fatal("It looks like you are trying to boot an Android " \
390 fatal("The MI_example protocol cannot implement Load/Store "
674 fatal("Don't know how to connect these system together")
710 fatal("Don't know how to connect DistEtherLink to this system")

Completed in 42 milliseconds

123456789