Searched refs:bits (Results 51 - 75 of 120) sorted by relevance

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/gem5/src/base/filters/
H A Dblock_bloom_filter.cc55 "number of bits in an address");
87 bits(addr, offsetBits + masksLSBs[i] + masksSizes[i] - 1,
H A Dmulti_bit_sel_bloom_filter.cc78 uint64_t value = bits(addr, std::numeric_limits<Addr>::digits - 1,
/gem5/src/arch/mips/
H A Ddsp.cc286 sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
313 sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
333 sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
533 int signa = bits(dspac, 63, 63);
534 int signb = bits(result, 63, 63);
538 if (signa == signb && bits(temp, 63, 63) != signa) {
600 int signa = bits(dspac, 63, 63);
601 int signb = bits(-result, 63, 63);
605 if (signa == signb && bits(temp, 63, 63) != signa) {
1010 if (bits(*dspct
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/gem5/src/arch/arm/insts/
H A Dmisc.cc92 if (bits(byteMask, 1, 0)) {
106 if (bits(byteMask, 3)) {
113 if (bits(byteMask, 2)) {
120 if (bits(byteMask, 1)) {
123 if (bits(byteMask, 0)) {
H A Dvfp.hh161 uint32_t bits; member in union:ArmISA::__anon3
164 return val.bits;
173 uint64_t bits; member in union:ArmISA::__anon4
176 return val.bits;
180 bitsToFp(uint64_t bits, float junk) argument
185 uint32_t bits; member in union:ArmISA::__anon5
187 val.bits = bits;
192 bitsToFp(uint64_t bits, double junk) argument
197 uint64_t bits; member in union:ArmISA::__anon6
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/gem5/src/dev/arm/
H A Dgic_v2.cc335 bits(cpuSgiPending[active_int], 7 + 8 * x, 8 * x);
485 getIntPriority(ctx, int_num) = bits(data, 7, 0);
486 getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
490 getIntPriority(ctx, int_num) = bits(data, 7, 0);
491 getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
492 getIntPriority(ctx, int_num + 2) = bits(data, 23, 16);
493 getIntPriority(ctx, int_num + 3) = bits(data, 31, 24);
516 cpuTarget[ix] = bits(data, 7, 0);
517 cpuTarget[ix+1] = bits(data, 15, 8);
518 cpuTarget[ix+2] = bits(dat
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H A Dgic_v3_its.cc538 const auto icid = bits(command.raw[2], 15, 0);
559 cte.valid = bits(command.raw[2], 63);
560 cte.rdBase = bits(command.raw[2], 50, 16);
562 const auto icid = bits(command.raw[2], 15, 0);
576 dte.valid = bits(command.raw[2], 63);
578 dte.ittRange = bits(command.raw[1], 4, 0);
611 itte.icid = bits(command.raw[2], 15, 0);
632 const auto pintid = bits(command.raw[1], 63, 32);
647 itte.icid = bits(command.raw[2], 15, 0);
656 const uint64_t rd1 = bits(comman
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H A Dgic_v2.hh114 /** Mask off SGI's when setting/clearing pending bits */
117 /** Mask for bits that config N:N mode in GICD_ICFGR's */
182 * interrupt enable bits for first 32 interrupts, 1b per interrupt */
186 * interrupt pending bits for first 32 interrupts, 1b per interrupt */
190 * interrupt active bits for first 32 interrupts, 1b per interrupt */
194 * interrupt group bits for first 32 interrupts, 1b per interrupt */
214 * interrupt enable bits for global interrupts
215 * 1b per interrupt, 32 bits per word, 31 words */
227 * interrupt pending bits for global interrupts
228 * 1b per interrupt, 32 bits pe
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/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64c.cpp72 return D::bits(fld) == D::bits(fldsp);
H A Drv64d.h42 bits(double d) function in namespace:D
56 return std::isnan(f) && (bits(f)&0x0008000000000000ULL) != 0;
62 return std::isnan(f) && (bits(f)&0x0008000000000000ULL) == 0;
H A Drv64f.h42 bits(float f) function in namespace:F
56 return std::isnan(f) && (bits(f)&0x00400000) != 0;
62 return std::isnan(f) && (bits(f)&0x00400000) == 0;
/gem5/src/arch/x86/
H A Dpagetable_walker.cc355 entry.patBit = bits(pte, 12);
376 entry.patBit = bits(pte, 12);
416 entry.patBit = bits(pte, 12);
437 entry.patBit = bits(pte, 7);
464 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
467 entry.patBit = bits(pte, 12);
505 entry.patBit = bits(pte, 7);
H A Dpagetable.hh73 // The size of the page this represents, in address bits.
175 entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
/gem5/ext/fputils/
H A Dfp80.c205 const fp80_t fp80 = BUILD_FP80(fp64.bits & FP64_SIGN_BIT,
210 const fp80_t fp80 = BUILD_FP80(fp64.bits & FP64_SIGN_BIT, 0, 0);
221 const fp80_t fp80 = BUILD_FP80(fp64.bits & FP64_SIGN_BIT,
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py147 bits = int(math.log(system.cache_line_size, 2))
148 if 2**bits != system.cache_line_size.value:
150 return bits
H A Druby_caches_MI_example.py144 bits = int(math.log(system.cache_line_size, 2))
145 if 2**bits != system.cache_line_size.value:
147 return bits
/gem5/src/arch/arm/
H A Dtable_walker.cc462 DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
513 (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2);
674 (bits(currState->vaddr, n + 26, 30) << 3);
681 (bits(currState->vaddr, n + 17, 21) << 3);
735 bits(addr, MaxPhysAddrRange - 1, currPhysAddrRange));
785 switch (bits(currState->vaddr, 63,48)) {
792 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
802 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
814 switch(bits(currState->vaddr, 63,48)) {
830 if (bits(currStat
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H A Dfaults.cc399 } else if ((bits(exc_class, 5, 3) != 4) ||
400 (bits(exc_class, 2) && bits(issVal, 24))) {
405 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
406 (bits(exc_class, 3, 0) != 0))) {
416 value |= bits(issVal, 19, 0);
528 // some bits are set differently if we have been routed to hyp mode
824 dir = bits(machInst, 21, 21);
825 op0 = bits(machInst, 20, 19);
826 op1 = bits(machIns
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/gem5/src/systemc/utils/
H A Dvcd.cc169 std::string msg = csprintf("'%s' has 0 bits", name);
582 str[i] = ::bits(val, TimeWidth - i - 1) ? '1' : '0';
614 str[i] = ::bits(val, w - i - 1) ? '1' : '0';
687 int bits = 0; local
688 while (count >> bits)
689 bits++;
691 addNewTraceVal<VcdTraceValInt<unsigned int>>(v, name, bits);
/gem5/src/arch/sparc/
H A Dua2005.cc51 // If PIL < 14, copy over the tm and sm bits
61 // Copy over any of the other bits that are set
160 // clear lower 7 bits on writes.
228 if (bits(val,2,2))
230 setMiscRegNoEffect(miscReg, bits(val,0,0));
231 if (!bits(val,0,0)) {
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/
H A Dsll.S38 # Verify that shifts only use bottom six bits
H A Dsllw.S38 # Verify that shifts only use bottom five bits
H A Dsra.S38 # Verify that shifts only use bottom five bits
H A Dsraw.S38 # Verify that shifts only use bottom five bits
H A Dsrl.S41 # Verify that shifts only use bottom five bits

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