Searched refs:Event (Results 51 - 75 of 86) sorted by relevance
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_parser.hh | 70 * Event triggered to check the value of the destination registers. Needed 75 struct TarmacParserRecordEvent: public Event
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/gem5/src/dev/arm/ |
H A D | pl111.hh | 169 * Event wrapper for dmaDone() 174 class DmaDoneEvent : public Event 181 : Event(), obj(*_obj) {}
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H A D | ufs_device.hh | 942 void writeDevice(Event* additional_action, bool toDisk, Addr start, 947 Event* additional_action); 1165 * Event after a read to clean up the UTP data structures
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/gem5/src/systemc/utils/ |
H A D | tracefile.hh | 119 const Event *event; 124 event(Event::getFromScEvent(_event))
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/gem5/src/cpu/simple/ |
H A D | timing.hh | 173 struct TickEvent : public Event 329 struct IprEvent : Event {
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/gem5/src/dev/net/ |
H A D | dist_iface.cc | 433 DistIface::RecvScheduler::init(Event *recv_done, Tick link_delay) 673 DistIface::recvThreadFunc(Event *recv_done, Tick link_delay) 719 DistIface::spawnRecvThread(const Event *recv_done, Tick link_delay) 725 const_cast<Event *>(recv_done), 787 DistIface::init(const Event *done_event, Tick link_delay)
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/gem5/src/dev/ |
H A D | dma_device.cc | 153 DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 202 DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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/gem5/src/gpu-compute/ |
H A D | tlb_coalescer.cc | 52 false, Event::CPU_Tick_Pri), 55 false, Event::Maximum_Pri)
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H A D | lds_state.hh | 118 class TickEvent: public Event
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H A D | gpu_tlb.hh | 382 class TLBEvent : public Event
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H A D | shader.cc | 57 false, Event::CPU_Tick_Pri),
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H A D | dispatcher.cc | 57 false, Event::CPU_Tick_Pri)
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/gem5/src/python/m5/ |
H A D | main.py | 408 e = event.create(trace.enable, event.Event.Debug_Enable_Pri) 415 e = event.create(trace.disable, event.Event.Debug_Enable_Pri)
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/gem5/src/systemc/core/ |
H A D | object.cc | 150 Event::getFromScEvent(event)->clearParent();
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/gem5/src/dev/serial/ |
H A D | uart8250.cc | 77 Uart8250::scheduleIntr(Event *event)
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/gem5/src/cpu/o3/ |
H A D | inst_queue.hh | 99 class FUCompletion : public Event {
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H A D | fetch.hh | 140 /* Event to delay delivery of a fetch translation result in case of 143 class FinishTranslationEvent : public Event 549 /** Event used to delay fault generation of translation faults */
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H A D | lsq_unit.hh | 382 void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); } 437 class WritebackEvent : public Event
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/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.cc | 79 false, Event::CPU_Tick_Pri),
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.cc | 55 false, Event::CPU_Tick_Pri),
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/gem5/src/cpu/ |
H A D | base.hh | 88 class CPUProgressEvent : public Event
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/gem5/src/base/ |
H A D | remote_gdb.cc | 179 : PCEvent(q, "HardBreakpoint Event", pc), 760 BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta) 769 BaseRemoteGDB::descheduleInstCommitEvent(Event *ev)
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/gem5/src/arch/arm/ |
H A D | table_walker.hh | 946 Event* LongDescEventByLevel[4]; 949 Request::Flags flags, int queueIndex, Event *event,
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/gem5/ext/testlib/ |
H A D | handlers.py | 362 self._shutdown = threading.Event()
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/gem5/src/cpu/kvm/ |
H A D | base.cc | 78 false, Event::CPU_Tick_Pri), 167 Event *startupEvent(
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Completed in 63 milliseconds
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