Searched hist:8551 (Results 1 - 8 of 8) sorted by relevance

/gem5/src/dev/arm/
H A Dgeneric_timer.hh10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
H A Dgeneric_timer.cc10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
H A DRealView.py10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
/gem5/src/arch/arm/
H A Dsystem.hh10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
H A Dsystem.cc10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
H A Disa.hh10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
H A Disa.cc10844:8551af601f75 Sat May 23 08:46:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Refactor and clean up the generic timer model

This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
/gem5/src/mem/
H A Drequest.hh8551:4e09d02322fb Tue Sep 13 01:06:00 EDT 2011 Daniel Johnson <daniel.johnson@arm.com> Mem: Allow ASID to be set after request is created.

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