Searched hist:56 (Results 151 - 175 of 501) sorted by relevance
/gem5/tests/testing/ | ||
H A D | tests.py | 12075:2f691b779441 Thu Jun 15 12:56:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Fix a typo for the default MI_example protocol Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3795 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 11482:2ca1efb451e4 Thu May 26 06:56:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> tests: Add test infrastructure as a Python module Implement gem5's test infrastructure as a Python module and a run script that can be used without scons. The new implementation has several features that were lacking from the previous test infrastructure such as support for multiple output formats, automatic runtime tracking, and better support for being run in a cluster environment. Tests consist of one or more steps (TestUnit). Units are run in two stages, the first a run stage and then a verify stage. Units in the verify stage are automatically skipped if any unit run stage wasn't run. The library currently contains TestUnit implementations that run gem5, diff stat files, and diff output files. Existing tests are implemented by the ClassicTest class and "just work". New tests can that don't rely on the old "run gem5 once and diff output" strategy can be implemented by subclassing the Test base class or ClassicTest. Test results can be output in multiple formats. The module currently supports JUnit, text (short and verbose), and Python's pickle format. JUnit output allows CI systems to automatically get more information about test failures. The pickled output contains all state necessary to reconstruct a tests results object and is mainly intended for the build system and CI systems. Since many JUnit parsers parsers assume that test suite names look like Java package names. We currently output path-like names with slashes separating components. Test names are translated according to these rules: * '.' -> '-" * '/' -> '.' The test tool, tests.py, supports the following features: * Test listing. Example: ./tests.py list arm/quick * Running tests. Example: ./tests.py run -o output.pickle --format pickle \ ../build/ARM/gem5.opt \ quick/se/00.hello/arm/linux/simple-timing * Displaying pickled results. Example: ./tests.py show --format summary *.pickle Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joel Hestness <jthestness@gmail.com> |
/gem5/src/mem/ | ||
H A D | port_proxy.hh | 14007:36f842f523c6 Wed May 01 20:56:00 EDT 2019 Gabe Black <gabeblack@google.com> arm, mem: Move the SecurePortProxy subclass into it's own file. The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> 8861:56d011130987 Wed Feb 29 04:47:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Make all the port proxy members const This is a trivial patch that merely makes all the member functions of the port proxies const. There is no good reason why they should not be, and this change only serves to make it explicit that they are not modified through their use. |
H A D | port_proxy.cc | 14007:36f842f523c6 Wed May 01 20:56:00 EDT 2019 Gabe Black <gabeblack@google.com> arm, mem: Move the SecurePortProxy subclass into it's own file. The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> 8861:56d011130987 Wed Feb 29 04:47:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Make all the port proxy members const This is a trivial patch that merely makes all the member functions of the port proxies const. There is no good reason why they should not be, and this change only serves to make it explicit that they are not modified through their use. |
/gem5/src/cpu/ | ||
H A D | activity.hh | 5804:34fe9bbc6705 Wed Jan 21 17:56:00 EST 2009 Nathan Binkert <nate@binkert.org> o3cpu: give a name to the activity recorder for better tracing |
H A D | pc_event.hh | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/src/sim/ | ||
H A D | voltage_domain.hh | 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5 Adds DVFS capabilities to gem5, by allowing users to specify lists for frequencies and voltages in SrcClockDomains and VoltageDomains respectively. A separate component, DVFSHandler, provides a small interface to change operating points of the associated domains. Clock domains will be linked to voltage domains and thus allow separate clock, but shared voltage lines. Currently all the valid performance-level updates are performed with a fixed transition latency as specified for the domain. Config file example: ... vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V']) tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster1.clk_domain.domain_id = 0 tsys.cluster2.clk_domain.domain_id = 1 tsys.cluster1.clk_domain.voltage_domain = vd tsys.cluster2.clk_domain.voltage_domain = vd tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain, tsys.cluster2.clk_domain] tsys.dvfs_handler.enable = True |
H A D | dvfs_handler.hh | 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5 Adds DVFS capabilities to gem5, by allowing users to specify lists for frequencies and voltages in SrcClockDomains and VoltageDomains respectively. A separate component, DVFSHandler, provides a small interface to change operating points of the associated domains. Clock domains will be linked to voltage domains and thus allow separate clock, but shared voltage lines. Currently all the valid performance-level updates are performed with a fixed transition latency as specified for the domain. Config file example: ... vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V']) tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster1.clk_domain.domain_id = 0 tsys.cluster2.clk_domain.domain_id = 1 tsys.cluster1.clk_domain.voltage_domain = vd tsys.cluster2.clk_domain.voltage_domain = vd tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain, tsys.cluster2.clk_domain] tsys.dvfs_handler.enable = True |
H A D | voltage_domain.cc | 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5 Adds DVFS capabilities to gem5, by allowing users to specify lists for frequencies and voltages in SrcClockDomains and VoltageDomains respectively. A separate component, DVFSHandler, provides a small interface to change operating points of the associated domains. Clock domains will be linked to voltage domains and thus allow separate clock, but shared voltage lines. Currently all the valid performance-level updates are performed with a fixed transition latency as specified for the domain. Config file example: ... vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V']) tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster1.clk_domain.domain_id = 0 tsys.cluster2.clk_domain.domain_id = 1 tsys.cluster1.clk_domain.voltage_domain = vd tsys.cluster2.clk_domain.voltage_domain = vd tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain, tsys.cluster2.clk_domain] tsys.dvfs_handler.enable = True |
/gem5/src/base/ | ||
H A D | inet.hh | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
H A D | hostinfo.cc | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | m5ops.isa | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/src/kern/ | ||
H A D | SConscript | 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc |
/gem5/src/arch/x86/insts/ | ||
H A D | microregop.cc | 6440:78d25904f66a Wed Aug 05 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix how the parity flag is computed. It's only for the lowest order byte, and I had the polarity wrong. |
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/ | ||
H A D | config.ini | 11946:8eb1f2595a92 Tue Apr 04 03:56:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Add a boat load of stats to the SPARC solaris boot regression. A large number of stats were added by the following change: commit 5350879f499470a2683dfec6cff021dd7ac20fa6 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Add power states to ClockedObject Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2 Reviewed-on: https://gem5-review.googlesource.com/2642 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | simout | 11946:8eb1f2595a92 Tue Apr 04 03:56:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Add a boat load of stats to the SPARC solaris boot regression. A large number of stats were added by the following change: commit 5350879f499470a2683dfec6cff021dd7ac20fa6 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Add power states to ClockedObject Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2 Reviewed-on: https://gem5-review.googlesource.com/2642 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/ | ||
H A D | simerr | 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/ | ||
H A D | simout | 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/ | ||
H A D | simout | 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/dev/arm/ | ||
H A D | timer_sp804.hh | 9806:3f262c18ad5d Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev/arm: get rid of AmbaDev namespace It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/src/mem/ruby/common/ | ||
H A D | Consumer.hh | 9557:8666e81607a6 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Fix warnings issued by clang 3.2svn (XCode 4.6) This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned. |
/gem5/src/proto/ | ||
H A D | packet.proto | 10107:524afa92d940 Fri Mar 07 15:56:00 EST 2014 Radhika Jagtap <radhika.jagtap@ARM.com> mem: Edit proto Packet and enhance the python script This patch changes the decode script to output the optional fields of the proto message Packet, namely id and flags. The flags field is set by the communication monitor. The id field is useful for CPU trace experiments, e.g. linking the fetch side to decode side. It had to be renamed because it clashes with a built in python function id() for getting the "identity" of an object. This patch also takes a few common function definitions out from the multiple scripts and adds them to a protolib python module. |
/gem5/src/arch/mips/isa/formats/ | ||
H A D | dsp.isa | 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/src/arch/x86/ | ||
H A D | remote_gdb.cc | 4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files. |
H A D | pagetable.hh | 4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files. |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | vfp.isa | 10205:3ca67d0e0e7e Thu Apr 17 17:56:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Make sure UndefinedInstructions are properly initialized |
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