Searched hist:4156 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/mem/cache/ | ||
| H A D | queue_entry.hh | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| H A D | write_queue_entry.hh | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| H A D | noncoherent_cache.cc | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| H A D | mshr.hh | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| H A D | cache.cc | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| H A D | base.cc | 13859:4156ac0c7257 Wed Jan 30 08:46:00 EST 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move Target to QueueEntry WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| /gem5/src/cpu/simple/ | ||
| H A D | base.cc | 4156:a4667c990e12 Mon Mar 05 11:13:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add x86 version of call to "decode" |
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