Searched hist:3969 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/cpu/minor/ | ||
| H A D | cpu.cc | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/ | ||
| H A D | BaseCPU.py | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base.cc | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base.hh | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | iew_impl.hh | 3969:77957f66c1d5 Thu Dec 28 14:35:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debug output out of ifdefs. |
| H A D | cpu.cc | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/simple/ | ||
| H A D | timing.cc | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | atomic.cc | 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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