Searched hist:2015 (Results 826 - 850 of 1505) sorted by relevance

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/gem5/configs/ruby/
H A DMESI_Two_Level.py11266:452e10b868ea Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> ruby: more flexible ruby tester support

This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests. This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code. Finally, the patch also includes better DPRINTFs for
debugging the tester.
11065:37e19af67f62 Sun Aug 30 01:24:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed. Each protocol
should now specify the value it needs.
11022:e6e3b7097810 Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Protocol changes for SimObject MessageBuffers
11019:fc1e41e88fd3 Fri Aug 14 01:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> ruby: Remove the RubyCache/CacheMemory latency

The RubyCache (CacheMemory) latency parameter is only used for top-level caches
instantiated for Ruby coherence protocols. However, the top-level cache hit
latency is assessed by the Sequencer as accesses flow through to the cache
hierarchy. Further, protocol state machines should be enforcing these cache hit
latencies, but RubyCaches do not expose their latency to any existng state
machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter
is superfluous for all caches. This is confusing for users.

As a step toward pushing L0/L1 cache hit latency into the top-level cache
controllers, move their latencies out of the RubyCache declarations and over to
their Sequencers. Eventually, these Sequencer parameters should be exposed as
parameters to the top-level cache controllers, which should assess the latency.
NOTE: Assessing these latencies in the cache controllers will require modifying
each to eliminate instantaneous Ruby hit callbacks in transitions that finish
accesses, which is likely a large undertaking.
/gem5/src/arch/arm/
H A DArmNativeTrace.py10663:fae54a666162 Sun Jan 25 07:22:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: Put all CPU instruction tracers in a single file
H A Dstage2_mmu.hh10912:b99a6662d7c2 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Decouple draining from the SimObject hierarchy

Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.

This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.

While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.

A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.
10873:7c972b9aea16 Sun Jun 21 15:48:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> arm: Cleanup arch headers to remove dma_device.hh dependency

Break the dependency on dma_device.hh by forward-declaring DmaPort in
the relevant header.
10820:e2a283400c43 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> arch, cpu: Do not forward snoops to table walker

This patch simplifies the overall CPU by changing the TLB caches such
that they do not forward snoops to the table walker port(s). Note that
only ARM and X86 are affected.

There is no reason for the ports to snoop as they do not actually take
any action, and from a performance point of view we are better of not
snooping more than we have to.

Should it at a later point be required to snoop for a particular TLB
design it is easy enough to add it back.
10717:4f8c1bd6fdb8 Mon Mar 02 04:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> arm: Share a port for the two table walker objects

This patch changes how the MMU and table walkers are created such that
a single port is used to connect the MMU and the TLBs to the memory
system. Previously two ports were needed as there are two table walker
objects (stage one and stage two), and they both had a port. Now the
port itself is moved to the Stage2MMU, and each TableWalker is simply
using the port from the parent.

By using the same port we also remove the need for having an
additional crossbar joining the two ports before the walker cache or
the L2. This simplifies the creation of the CPU cache topology in
BaseCPU.py considerably. Moreover, for naming and symmetry reasons,
the TLB walker port is connected through the stage-one table walker
thus making the naming identical to x86. Along the same line, we use
the stage-one table walker to generate the master id that is used by
all TLB-related requests.
/gem5/src/dev/net/
H A Detherbus.hh11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
H A Detherdevice.hh11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
H A Detherlink.hh11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
H A Dns_gige.hh11263:8dcc6b40f164 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move network devices to src/dev/net/
/gem5/src/mem/probes/
H A DMemTraceProbe.py10996:d48fda705f4d Tue Aug 04 05:29:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> mem: Move trace functionality from the CommMonitor to a probe

This changeset moves the access trace functionality from the
CommMonitor into a separate probe. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.

This patch moves the dependency on Google's Protocol Buffers library
from the CommMonitor to the MemTraceProbe, which means that the
CommMonitor (including stack distance profiling) no long depends on
it.
/gem5/src/arch/generic/
H A DBaseTLB.py10687:276da6265ab8 Wed Feb 11 10:23:00 EST 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> sim: Move the BaseTLB to src/arch/generic/

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
/gem5/src/mem/cache/
H A Dmshr.cc11286:2071db8f864b Thu Dec 31 09:33:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Do not allocate space for packet data if not needed

This patch looks at the request and response command to determine if
either actually has any data payload, and if not, we do not allocate
any space for packet data.

The only tricky case is where the command type is changed as part of
the MSHR functionality. In these cases where the original packet had
no data, but the new packet does, we need to explicitly call
allocate().
11284:b3926db25371 Thu Dec 31 09:32:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Make cache terminology easier to understand

This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
11279:3fd1142adad9 Mon Dec 28 11:14:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Explicitly check MSHR snoops for cases not dealt with

Add a sanity check to make it explicit that we currently do not allow
an I/O coherent agent to directly issue writes into the coherent part
of the memory system (it has to go via a cache, and get transformed
into a read ex, upgrade or invalidation).
11278:18411ccc4f3c Mon Dec 28 11:14:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Remove unused cache squash functionality

This patch removes the unused squash function from the MSHR queue, and
the associated (and also unused) threadNum member from the MSHR.
11271:f4ad5be63ba8 Thu Dec 17 17:07:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Fix memory allocation bug in deferred snoop handling

This patch fixes a corner case in the deferred snoop handling, where
requests ended up being used by multiple packets with different
lifetimes, and inadvertently got deleted while they were still in use.
11197:f8fdd931e674 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Add cache clusivity

This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.

The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.

This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.

Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.

The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
11177:524c44cf8278 Thu Oct 29 08:48:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Clarify cache MSHR handling on fill

This patch addresses the upgrading of deferred targets in the MSHR,
and makes it clearer by explicitly calling out what is happening
(deferred targets are promoted if we get exclusivity without asking
for it).
11083:61b329833f74 Fri Sep 04 13:14:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Avoid setting markPending if not needed

In cases where a newly added target does not have any upstream MSHR to
mark as downstreamPending, remember that nothing is marked. This
allows us to avoid attempting to find the MSHR as part of the clearing
of downstreamPending.
10922:5ee72f4b2931 Mon Jul 13 08:46:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Fix (ab)use of emplace to avoid temporary object creation
10826:fe0b1f40ea5a Tue Mar 17 07:50:00 EDT 2015 Stephan Diestelhorst <stephan.diestelhorst@ARM.com> mem: Create a request copy for deferred snoops

Sometimes, we need to defer an express snoop in an MSHR, but the original
request might complete and deallocate the original pkt->req. In those cases,
create a copy of the request so that someone who is inspecting the delayed
snoop can also inspect the request still. All of this is rather hacky, but the
allocation / linking and general life-time management of Packet and Request is
rather tricky. Deleting the copy is another tricky area, testing so far has
shown that the right copy is deleted at the right time.
/gem5/src/mem/cache/prefetch/
H A Daccess_map_pattern_matching.cc13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher

Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.

Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already
in gem5).

Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Reviewed-on: https://gem5-review.googlesource.com/c/16383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dsignature_path.cc13553:047def1fa787 Thu Nov 29 10:59:00 EST 2018 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Signature Path Prefetcher

Related paper:
Lookahead Prefetching with Signature Path
J Kim, PV Gratz, ALN Reddy
The 2nd Data Prefetching Championship (DPC2), 2015

Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11
Reviewed-on: https://gem5-review.googlesource.com/c/14737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dsignature_path.hh13553:047def1fa787 Thu Nov 29 10:59:00 EST 2018 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Signature Path Prefetcher

Related paper:
Lookahead Prefetching with Signature Path
J Kim, PV Gratz, ALN Reddy
The 2nd Data Prefetching Championship (DPC2), 2015

Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11
Reviewed-on: https://gem5-review.googlesource.com/c/14737
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/python/m5/util/
H A Dfdthelper.py12469:ea3fefba5a72 Wed Dec 16 10:43:00 EST 2015 Glenn Bergmans <glenn.bergmans@arm.com> arm: DT autogeneration - Device Tree generation methods

This patch adds an extra layer to the pyfdt library such that usage
gets easier and device tree nodes can be specified in less code,
without limiting original usage. Note to not import both the pyfdt
and fdthelper in the same namespace (but generally fdthelper is all
you need, because it supplies the same classes even when they are not
extended in any way)

Also, this patch lays out the primary functionality for generating a
device tree, where every SimObject gets an empty generateDeviceTree
method and ArmSystems loop over their children in an effort to merge
all the nodes. Devices are implemented in other patches.

Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5962
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/ruby/common/
H A DAddress.cc11118:75c1e564a725 Fri Sep 18 14:27:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
H A DDataBlock.hh11305:78c1e4f5dfc5 Mon Jul 20 10:15:00 EDT 2015 Blake Hechtman <blake.hechtman@amd.com> mem: misc flags for AMD gpu model

This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.
11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040
11042:d34a75cb3646 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: DataBlock: adds a comment
/gem5/src/sim/
H A Dvoltage_domain.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
/gem5/src/cpu/kvm/
H A Dx86_cpu.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
10653:e3fc6bc7f97e Thu Jan 22 05:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Clean up Request initialisation

This patch tidies up how we create and set the fields of a Request. In
essence it tries to use the constructor where possible (as opposed to
setPhys and setVirt), thus avoiding spreading the information across a
number of locations. In fact, setPhys is made private as part of this
patch, and a number of places where we callede setVirt instead uses
the appropriate constructor.
/gem5/src/dev/mips/
H A Dmalta_io.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class

Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:

* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.

* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.

* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).

* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.

* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
10631:6d6bfdb036ce Sat Jan 03 18:51:00 EST 2015 Cagdas Dirik <cdirik@micron.com> dev: prevent RTC events firing before startup

This change includes edits to MC146818 timer to prevent RTC events
firing before startup to comply with SimObject initialization call sequence.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dsimout11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets
10798:74e3c7359393 Wed Apr 22 23:22:00 EDT 2015 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for previous changeset

Very small differences in IQ-specific O3 stats.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/
H A Dstats.txt11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling
11239:3be64e1f80ed Thu Dec 03 19:19:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to RealView platform code
11214:966091379ded Mon Nov 16 05:58:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: remove wb_penalized and wb_penalized_rate
11201:b1bd4afb6b16 Fri Nov 06 03:26:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to match cache changes
11138:a611a23c8cc2 Fri Sep 25 07:27:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect snoop-filter changes
11014:863d314f6356 Fri Aug 07 10:39:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update ARM stats to include programmable oscillators
10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
10855:117db3a0d78c Tue May 26 03:21:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> arm, stats: Update stats to reflect reduction in misc reg reads
10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10798:74e3c7359393 Wed Apr 22 23:22:00 EDT 2015 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for previous changeset

Very small differences in IQ-specific O3 stats.
/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/
H A Dconfig.ini11103:38f6188421e0 Tue Sep 15 09:14:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changesets including d0934b57735a
10901:8cfa8dac39fe Sun Jul 05 21:26:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: x86: update stats missed out on in preivous changeset
10645:cd95d4d51659 Sat Jan 10 19:06:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to recent changesets.
/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/
H A Dconfig.ini11103:38f6188421e0 Tue Sep 15 09:14:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent changesets including d0934b57735a
10901:8cfa8dac39fe Sun Jul 05 21:26:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: x86: update stats missed out on in preivous changeset
10645:cd95d4d51659 Sat Jan 10 19:06:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: changes due to recent changesets.
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/
H A Dstats.txt10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/
H A Dstats.txt10827:7f5467f2f8b8 Tue May 05 03:22:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache changes
10812:bacaefeb126a Thu Apr 30 15:17:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: arm: updates
10726:8a20e2a1562d Mon Mar 02 05:04:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

Completed in 128 milliseconds

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