Searched hist:2011 (Results 601 - 625 of 897) sorted by relevance

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/gem5/src/arch/alpha/
H A Dpagetable.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
H A Dremote_gdb.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/isa/decoder/
H A Dx87.isa8106:4a194d4f6fb0 Wed Mar 02 03:41:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Decode the mysterious and elusive ffreep x87 instruction.

The internet says this instruction was created by accident when an Intel CPU
failed to decode x87 instructions properly. It's been documented on a few rare
occasions and has generally worked to ensure backwards compatability. One
source claims that the gcc toolchain is basically the only thing that emits
it, and that emulators/binary translators like qemu and bochs implement it.

We won't actually implement it here since we're hardly implementing any other
x87 instructions either. If we were to implement it, it would behave the same
as ffree but then also pop the register stack.

http://www.pagetable.com/?p=16
/gem5/src/dev/alpha/
H A Dtsunami.hh8741:491297d019f3 Fri Sep 30 03:29:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove System::platform and Platform::intrFrequency.

In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
/gem5/src/mem/ruby/common/
H A DAddress.cc8091:04078b1214dd Fri Feb 25 18:51:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.
H A DConsumer.hh7973:e5550966464a Mon Feb 14 17:14:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three loops -

loop on number of virtual networks
loop on number of incoming links
loop till all messages for this (link, network) have been routed

With an 8 processor mesh network and Hammer protocol, about 11-12% of the
was observed to have been spent in this function, which is the highest
amongst all the functions. It was found that the innermost loop is executed
about 45 times per invocation of the wakeup function, when each invocation
of the wakeup function processes just about one message.

The patch tries to do away with the redundant executions of the innermost
loop. Counters have been added for each virtual network that record the
number of messages that need to be routed for that virtual network. The
inner loops are only executed when the number of messages for that particular
virtual network > 0. This does away with almost 80% of the executions of the
innermost loop. The function now consumes about 5-6% of the total execution
time.
/gem5/src/mem/slicc/ast/
H A DInPortDeclAST.py7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.
/gem5/src/base/
H A Doutput.hh8634:8390f2d80227 Thu Dec 01 03:15:00 EST 2011 Chris Emmons <chris.emmons@arm.com> Output: Add hierarchical output support and cleanup existing codebase.
H A Dhostinfo.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/mips/linux/
H A Dlinux.hh8600:b0d7c64ada19 Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: implement MAP_FIXED option to mmap()
H A Dprocess.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/kern/linux/
H A Devents.hh8143:b0b94a7b7c1f Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Detect and skip udelay() functions in linux kernel.

This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
/gem5/src/sim/
H A DRoot.py7861:4ebff121cc0e Wed Jan 19 14:48:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Time: Add a mechanism to prevent M5 from running faster than real time.

M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
/gem5/src/base/loader/
H A Draw_object.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
H A Decoff_object.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/cpu/o3/
H A Dbase_dyn_inst.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dscoreboard.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/cpu/
H A Dprofile.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dintr_control.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/insts/
H A Dmicroldstop.hh8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
/gem5/src/arch/x86/isa/
H A Dspecialize.isa8250:de679a068dd8 Sat Apr 23 18:02:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: When decoding a memory only inst, fault on reg encodings, don't assert.

This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.
/gem5/src/arch/sparc/isa/formats/
H A Dunimp.isa8565:d9b69f03e7af Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove #if FULL_SYSTEMs from the ISA description.
/gem5/src/arch/sparc/
H A Dutility.hh8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.
8300:eb279d6e08a2 Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified. Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7878:d3e6ebcccabf Fri Feb 04 00:47:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
/gem5/src/dev/
H A Dmc146818.hh7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/arch/sparc/isa/formats/mem/
H A Dutil.isa8778:fbaf6af0be93 Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove the last uses of FULL_SYSTEM from SPARC.
8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
8342:77d12d8f7971 Thu Jun 09 01:34:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here

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