Searched hist:2007 (Results 401 - 425 of 895) sorted by relevance
/gem5/src/dev/alpha/ | ||
H A D | tsunami_cchip.cc | 4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch 4885:385a051ad874 Sat Jul 14 03:09:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Merge of DPRINTF fixes from head. 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4739:9f8edf47aeca Sat Jul 14 14:48:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix & tweak DPRINTFs for tracediff w/new cache code. Note that we should *not* print pointer values in DPRINTFs as these needlessly clutter tracediff output. 4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore |
H A D | tsunami_io.cc | 4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 3943:68e673d2db04 Sun Jan 28 13:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Stick the conversion of python to unix time with all of the other param code so that other functions can use it as well. 3932:62e915bb6704 Thu Jan 25 14:59:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Instead of passing an int to represent time between python and C++ pass the tuple of python's struct_time and interpret that. Fixes a problem where the local timezone leaked into the time calculation. Also fix things so that the unix, python, and RTC data sheets all get the right time. Provide both years since 1900 and BCD two digit year. Put the date back at 1/1/2006 for now. 3885:fd4067a5b903 Wed Jan 03 13:12:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Add 'Time' as a parameter type that can accept various formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit |
/gem5/src/dev/ | ||
H A D | isa_fake.cc | 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 5012:c0a28154d002 Mon Aug 27 00:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge with head 4986:b7c82ad6b3ef Fri Aug 24 16:39:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Mem: Make errors in the memory system be responses, not requests. Fixes cache handling of error responses. 4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. |
/gem5/src/base/ | ||
H A D | trace.hh | 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. 4042:dbd98b2264ed Fri Feb 09 17:39:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Trace ParamContext and give python direct access to enabling/disabling tracing. Command line is unchanged except for the removal of --trace-cycle since it's not so clear what that means. 4041:f42c73e7e639 Thu Feb 08 23:59:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Use c99 variadic macros for non gnu compilers 4039:b910b61a52b9 Thu Feb 08 01:11:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the gross operator,()/variadic macro hack that made ccprintf and friends work, turn it into a normal function (though it still has a slightly strange implementation.) All instances of variadic macros are not yet removed, but I know how, and it will happen. One side effect of this new implementation is that a cprintf statement can now only have 16 parameters, though it's easy enough to raise this number if needed. 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc |
/gem5/src/base/loader/ | ||
H A D | object_file.cc | 5223:5f581fe175ce Wed Nov 14 06:18:00 EST 2007 Korey Sewell <ksewell@umich.edu> remove unnecessary debug messages I added 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 5070:3d6a1e37b944 Tue Sep 11 00:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Loader: Error if a TLS section is found in the binary. 3930:f96f7e258255 Fri Jan 26 18:49:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Merge zeep.pool:/z/saidi/work/m5.newmem into zeep.pool:/z/saidi/work/m5.suncc 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc 3917:a6cc1842f529 Mon Jan 22 16:14:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> check if an executable is dynamic and die if it is Only implemented for ELf. Someone might want to implement it for ecoff and some point src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.cc: src/base/loader/object_file.hh: add a function to check if an executable is dynamic src/sim/process.cc: check if an executable is dynamic and die if it is |
/gem5/src/arch/x86/ | ||
H A D | tlb.hh | 5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh. 5242:280a99136427 Mon Nov 12 17:39:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement tlb invalidation and make it happen some of the times it should. 5237:6c819dbe8045 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the page table walker, TLB, and related faults. 5236:0050ad4fb3ef Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement a page table walker. 5140:2fd7f8477b4c Sun Oct 07 21:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the x86 tlb. 5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging. 5118:f1b1cb6d0fbe Wed Oct 03 01:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the ldst microop and put it in existing microcode where appropriate. 5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile. 5038:c996bb7f1a6d Fri Aug 31 16:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get x86 to compile again after the simobject constructor change. 5019:2762e580f5db Tue Aug 28 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: De-templatize the GenericTLB class. |
H A D | pagetable.cc | 5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. 5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging. |
H A D | X86System.py | 5299:e61b9f2a9732 Sun Dec 02 02:09:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move startup code to the system object to initialize a Linux system. 5132:ad5e94876bfc Sun Oct 07 20:48:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make an x86 system object. |
/gem5/src/mem/ | ||
H A D | tport.cc | 4970:d0ed47928f9c Sun Aug 12 19:43:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> MemorySystem: Fix the use of ?: to produce correct results. 4929:6db35d0c81c6 Sun Jul 29 23:17:00 EDT 2007 Steve Reinhardt <stever@gmail.com> memory system: fix functional access bug. Make sure not to keep processing functional accesses after they've been responded to. Also use checkFunctional() return value instead of checking packet command field where possible, mostly just for consistency. 4911:3a0ee63f490c Wed Jul 25 01:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Don't delete request at target... requester still needs it. 4874:cdae9adbd276 Sat Jun 30 20:51:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of obsolete fixPacket() functions. Handled by Packet::checkFunctional() now. 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4670:54ac1fb49a26 Wed Jun 27 01:23:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Handle deferred snoops better. 4666:5d110d024fcf Mon Jun 25 09:47:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of requestCauses. Use timestamped queue to make sure we don't re-request bus prematurely. Use callback to avoid calling sendRetry() recursively within recvTiming. 4626:ed8aacb19c03 Sun Jun 17 20:27:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> More major reorg of cache. Seems to work for atomic mode now, timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. 4493:0757d7c8a0e5 Wed May 30 01:53:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> tport.cc: Oops... forgot to update call site after changing function argument semantics. src/mem/tport.cc: Oops... forgot to update call site after changing function argument semantics. 4492:75dabb0392ee Wed May 30 01:23:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> A little more cleanup & refactoring of SimpleTimingPort. Make it a better base class for cache ports. |
/gem5/src/dev/sparc/ | ||
H A D | t1000.hh | 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4000:9bf49767a9e4 Tue Jan 30 18:25:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make SPARC checkpointing work src/arch/sparc/floatregfile.cc: Fix serialization for fpreg src/arch/sparc/intregfile.cc: fix serialization for intreg src/arch/sparc/miscregfile.cc: fix serialization from miscreg src/arch/sparc/pagetable.cc: fix serialization for page table src/arch/sparc/regfile.cc: need to serialize nnpc src/arch/sparc/tlb.cc: write serialization code for tlb src/cpu/base.cc: provide a way to find the thread number a context is serialize the instruction counter src/cpu/base.hh: provide a way to find the thread number a context is and given a thread number find a context pointer src/cpu/cpuevent.hh: provide method to get thread context from a cpu event for serialization src/dev/sparc/t1000.cc: src/dev/sparc/t1000.hh: nothing to serialize in t1000 src/sim/serialize.cc: src/sim/serialize.hh: Make findObj() work (it hasn't since we did the python conversion stuff) |
H A D | iob.hh | 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4104:10b99ef0a7ff Sat Mar 03 19:02:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Add Iob and remove the fake device configs/common/FSConfig.py: add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy |
/gem5/src/arch/sparc/isa/ | ||
H A D | bitfields.isa | 4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha 3991:00bbda284575 Mon Jan 29 22:46:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fix the FCMPCC bitfield. |
/gem5/src/arch/x86/linux/ | ||
H A D | linux.cc | 4759:60e820a327db Tue Jul 24 18:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a tgt_iovec structure to support writev, change the name of X86Linux to X86Linux64, add some syscalls. 4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it. src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. |
H A D | process.hh | 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it. src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. |
/gem5/ext/libelf/ | ||
H A D | elf_common.h | 4494:b7c909b5a5e9 Wed May 30 17:08:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Fix compiling on Solaris since Nate's libelf change SConstruct: export env after we've set CC/CXX ext/libelf/SConscript: pull in the CC/CXX variables from env. Use gm4 if it exists ext/libelf/elf_begin.c: ext/libelf/libelf_allocate.c: include errno.h instead of sys/errno.h ext/libelf/elf_common.h: use the more standard uintX_t ext/libelf/elf_strptr.c: ext/libelf/elf_update.c: include sysmacros.h on Solaris for roundup() 4484:7c56a6c9c265 Sat May 26 21:15:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Get rid of GNU libelf and its autoconf nastiness and replace it with FreeBSD's implementation |
/gem5/src/arch/mips/ | ||
H A D | faults.cc | 5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers 5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers 5250:42577371ff31 Thu Nov 15 03:10:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" 5224:0e354459fb8a Wed Nov 14 06:24:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". 4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. |
H A D | interrupts.hh | 5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
H A D | interrupts.cc | 5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
/gem5/src/arch/alpha/linux/ | ||
H A D | process.hh | 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 4110:ed2a23e01898 Wed Feb 28 11:29:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> The "hostname" variable isn't used in the process classes. It should be removed from the other ones as well. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | decoder.isa | 4276:f0030662ee2a Wed Mar 21 15:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are. 4275:8a37341c7507 Wed Mar 21 15:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Missed a const |
/gem5/util/m5/ | ||
H A D | m5op_sparc.S | 4098:9b57d3d6af2a Sat Feb 24 22:05:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make m5 readfile work on solaris... we can have a solaris regression soon! src/arch/sparc/isa/decoder.isa: add readfile and break to sparc decoder src/arch/sparc/isa/operands.isa: fix O0-O5 operands registers util/m5/Makefile.sparc: Make sparc makefile compile a 64bit binary util/m5/m5.c: readfile was in here twice, once will be sufficient I think util/m5/m5op_sparc.S: implement readfile and debugbreak 4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha |
H A D | Makefile.sparc | 4098:9b57d3d6af2a Sat Feb 24 22:05:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make m5 readfile work on solaris... we can have a solaris regression soon! src/arch/sparc/isa/decoder.isa: add readfile and break to sparc decoder src/arch/sparc/isa/operands.isa: fix O0-O5 operands registers util/m5/Makefile.sparc: Make sparc makefile compile a 64bit binary util/m5/m5.c: readfile was in here twice, once will be sufficient I think util/m5/m5op_sparc.S: implement readfile and debugbreak 4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha |
/gem5/src/arch/x86/isa/formats/ | ||
H A D | syscall.isa | 4806:e0c57a8e197c Mon Jul 30 16:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: missed a file which adds a "fold" bit. 4712:79b4c64296ce Thu Jul 19 18:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> x86 fixes Make the emulation environment consider the rex prefix. Implement and hook in forms of j, jmp, cmp, syscall, movzx Added a format for an instruction to carry a call to the SE mode syscalls system Made memory instructions which refer to the rip do so directly Made the operand size overridable in the microassembly Made the "ext" field of register operations 16 bits to hold a sparse encoding of flags to set or conditions to predicate on Added an explicit "rax" operand for the syscall format Implemented syscall returns. |
/gem5/src/arch/x86/isa/insts/general_purpose/ | ||
H A D | semaphores.py | 5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really). Also clean things up as much as possible so that faulting won't break an instruction. More microops which verify addresses are needed. 5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. |
/gem5/src/arch/x86/isa/insts/system/ | ||
H A D | msrs.py | 5243:4228b7b5704b Mon Nov 12 17:39:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement. 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
Completed in 134 milliseconds