1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Ron Dreslinski
30 */
31
32/** @file
33 * Emulation of the Tsunami CChip CSRs
34 */
35
36#include "dev/alpha/tsunami_cchip.hh"
37
38#include <deque>
39#include <string>
40#include <vector>
41
42#include "arch/alpha/ev5.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/intr_control.hh"
46#include "cpu/thread_context.hh"
47#include "debug/IPI.hh"
48#include "debug/Tsunami.hh"
49#include "dev/alpha/tsunami.hh"
50#include "dev/alpha/tsunamireg.h"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53#include "mem/port.hh"
54#include "params/TsunamiCChip.hh"
55#include "sim/system.hh"
56
57//Should this be AlphaISA?
58using namespace TheISA;
59
60TsunamiCChip::TsunamiCChip(const Params *p)
61    : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami)
62{
63    drir = 0;
64    ipint = 0;
65    itint = 0;
66
67    for (int x = 0; x < Tsunami::Max_CPUs; x++)
68    {
69        dim[x] = 0;
70        dir[x] = 0;
71    }
72
73    //Put back pointer in tsunami
74    tsunami->cchip = this;
75}
76
77Tick
78TsunamiCChip::read(PacketPtr pkt)
79{
80    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
81
82    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
83
84    Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
85    Addr daddr = (pkt->getAddr() - pioAddr);
86
87    switch (pkt->getSize()) {
88
89      case sizeof(uint64_t):
90          pkt->setLE<uint64_t>(0);
91
92          if (daddr & TSDEV_CC_BDIMS)
93          {
94              pkt->setLE(dim[(daddr >> 4) & 0x3F]);
95              break;
96          }
97
98          if (daddr & TSDEV_CC_BDIRS)
99          {
100              pkt->setLE(dir[(daddr >> 4) & 0x3F]);
101              break;
102          }
103
104          switch(regnum) {
105              case TSDEV_CC_CSR:
106                  pkt->setLE(0x0);
107                  break;
108              case TSDEV_CC_MTR:
109                  panic("TSDEV_CC_MTR not implemeted\n");
110                   break;
111              case TSDEV_CC_MISC:
112                  pkt->setLE(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
113                                     (pkt->req->contextId() & 0x3));
114                  // currently, FS cannot handle MT so contextId and
115                  // cpuId are effectively the same, don't know if it will
116                  // matter if FS becomes MT enabled.  I suspect no because
117                  // we are currently able to boot up to 64 procs anyway
118                  // which would render the CPUID of this register useless
119                  // anyway
120                  break;
121              case TSDEV_CC_AAR0:
122              case TSDEV_CC_AAR1:
123              case TSDEV_CC_AAR2:
124              case TSDEV_CC_AAR3:
125                  pkt->setLE(0);
126                  break;
127              case TSDEV_CC_DIM0:
128                  pkt->setLE(dim[0]);
129                  break;
130              case TSDEV_CC_DIM1:
131                  pkt->setLE(dim[1]);
132                  break;
133              case TSDEV_CC_DIM2:
134                  pkt->setLE(dim[2]);
135                  break;
136              case TSDEV_CC_DIM3:
137                  pkt->setLE(dim[3]);
138                  break;
139              case TSDEV_CC_DIR0:
140                  pkt->setLE(dir[0]);
141                  break;
142              case TSDEV_CC_DIR1:
143                  pkt->setLE(dir[1]);
144                  break;
145              case TSDEV_CC_DIR2:
146                  pkt->setLE(dir[2]);
147                  break;
148              case TSDEV_CC_DIR3:
149                  pkt->setLE(dir[3]);
150                  break;
151              case TSDEV_CC_DRIR:
152                  pkt->setLE(drir);
153                  break;
154              case TSDEV_CC_PRBEN:
155                  panic("TSDEV_CC_PRBEN not implemented\n");
156                  break;
157              case TSDEV_CC_IIC0:
158              case TSDEV_CC_IIC1:
159              case TSDEV_CC_IIC2:
160              case TSDEV_CC_IIC3:
161                  panic("TSDEV_CC_IICx not implemented\n");
162                  break;
163              case TSDEV_CC_MPR0:
164              case TSDEV_CC_MPR1:
165              case TSDEV_CC_MPR2:
166              case TSDEV_CC_MPR3:
167                  panic("TSDEV_CC_MPRx not implemented\n");
168                  break;
169              case TSDEV_CC_IPIR:
170                  pkt->setLE(ipint);
171                  break;
172              case TSDEV_CC_ITIR:
173                  pkt->setLE(itint);
174                  break;
175              default:
176                  panic("default in cchip read reached, accessing 0x%x\n");
177           } // uint64_t
178
179      break;
180      case sizeof(uint32_t):
181      case sizeof(uint16_t):
182      case sizeof(uint8_t):
183      default:
184        panic("invalid access size(?) for tsunami register!\n");
185    }
186    DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
187            regnum, pkt->getSize(), pkt->getLE<uint64_t>());
188
189    pkt->makeAtomicResponse();
190    return pioDelay;
191}
192
193Tick
194TsunamiCChip::write(PacketPtr pkt)
195{
196    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
197    Addr daddr = pkt->getAddr() - pioAddr;
198    Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
199
200
201    assert(pkt->getSize() == sizeof(uint64_t));
202
203    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n",
204            pkt->getAddr(), pkt->getLE<uint64_t>());
205
206    bool supportedWrite = false;
207
208
209    if (daddr & TSDEV_CC_BDIMS)
210    {
211        int number = (daddr >> 4) & 0x3F;
212
213        uint64_t bitvector;
214        uint64_t olddim;
215        uint64_t olddir;
216
217        olddim = dim[number];
218        olddir = dir[number];
219        dim[number] = pkt->getLE<uint64_t>();
220        dir[number] = dim[number] & drir;
221        for (int x = 0; x < Tsunami::Max_CPUs; x++)
222        {
223            bitvector = ULL(1) << x;
224            // Figure out which bits have changed
225            if ((dim[number] & bitvector) != (olddim & bitvector))
226            {
227                // The bit is now set and it wasn't before (set)
228                if ((dim[number] & bitvector) && (dir[number] & bitvector))
229                {
230                    tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
231                    DPRINTF(Tsunami, "dim write resulting in posting dir"
232                            " interrupt to cpu %d\n", number);
233                }
234                else if ((olddir & bitvector) &&
235                        !(dir[number] & bitvector))
236                {
237                    // The bit was set and now its now clear and
238                    // we were interrupting on that bit before
239                    tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
240                    DPRINTF(Tsunami, "dim write resulting in clear"
241                            " dir interrupt to cpu %d\n", number);
242
243                }
244
245
246            }
247        }
248    } else {
249        switch(regnum) {
250          case TSDEV_CC_CSR:
251              panic("TSDEV_CC_CSR write\n");
252          case TSDEV_CC_MTR:
253              panic("TSDEV_CC_MTR write not implemented\n");
254          case TSDEV_CC_MISC:
255            uint64_t ipreq;
256            ipreq = (pkt->getLE<uint64_t>() >> 12) & 0xF;
257            //If it is bit 12-15, this is an IPI post
258            if (ipreq) {
259                reqIPI(ipreq);
260                supportedWrite = true;
261            }
262
263            //If it is bit 8-11, this is an IPI clear
264            uint64_t ipintr;
265            ipintr = (pkt->getLE<uint64_t>() >> 8) & 0xF;
266            if (ipintr) {
267                clearIPI(ipintr);
268                supportedWrite = true;
269            }
270
271            //If it is the 4-7th bit, clear the RTC interrupt
272            uint64_t itintr;
273              itintr = (pkt->getLE<uint64_t>() >> 4) & 0xF;
274            if (itintr) {
275                  clearITI(itintr);
276                supportedWrite = true;
277            }
278
279              // ignore NXMs
280              if (pkt->getLE<uint64_t>() & 0x10000000)
281                  supportedWrite = true;
282
283            if (!supportedWrite)
284                  panic("TSDEV_CC_MISC write not implemented\n");
285
286            break;
287            case TSDEV_CC_AAR0:
288            case TSDEV_CC_AAR1:
289            case TSDEV_CC_AAR2:
290            case TSDEV_CC_AAR3:
291                panic("TSDEV_CC_AARx write not implemeted\n");
292            case TSDEV_CC_DIM0:
293            case TSDEV_CC_DIM1:
294            case TSDEV_CC_DIM2:
295            case TSDEV_CC_DIM3:
296                int number;
297                if (regnum == TSDEV_CC_DIM0)
298                    number = 0;
299                else if (regnum == TSDEV_CC_DIM1)
300                    number = 1;
301                else if (regnum == TSDEV_CC_DIM2)
302                    number = 2;
303                else
304                    number = 3;
305
306                uint64_t bitvector;
307                uint64_t olddim;
308                uint64_t olddir;
309
310                olddim = dim[number];
311                olddir = dir[number];
312                dim[number] = pkt->getLE<uint64_t>();
313                dir[number] = dim[number] & drir;
314                for (int x = 0; x < 64; x++)
315                {
316                    bitvector = ULL(1) << x;
317                    // Figure out which bits have changed
318                    if ((dim[number] & bitvector) != (olddim & bitvector))
319                    {
320                        // The bit is now set and it wasn't before (set)
321                        if ((dim[number] & bitvector) && (dir[number] & bitvector))
322                        {
323                          tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
324                          DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
325                        }
326                        else if ((olddir & bitvector) &&
327                                !(dir[number] & bitvector))
328                        {
329                            // The bit was set and now its now clear and
330                            // we were interrupting on that bit before
331                            tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
332                          DPRINTF(Tsunami, "dim write resulting in clear"
333                                    " dir interrupt to cpu %d\n",
334                                    x);
335
336                        }
337
338
339                    }
340                }
341                break;
342            case TSDEV_CC_DIR0:
343            case TSDEV_CC_DIR1:
344            case TSDEV_CC_DIR2:
345            case TSDEV_CC_DIR3:
346                panic("TSDEV_CC_DIR write not implemented\n");
347            case TSDEV_CC_DRIR:
348                panic("TSDEV_CC_DRIR write not implemented\n");
349            case TSDEV_CC_PRBEN:
350                panic("TSDEV_CC_PRBEN write not implemented\n");
351            case TSDEV_CC_IIC0:
352            case TSDEV_CC_IIC1:
353            case TSDEV_CC_IIC2:
354            case TSDEV_CC_IIC3:
355                panic("TSDEV_CC_IICx write not implemented\n");
356            case TSDEV_CC_MPR0:
357            case TSDEV_CC_MPR1:
358            case TSDEV_CC_MPR2:
359            case TSDEV_CC_MPR3:
360                panic("TSDEV_CC_MPRx write not implemented\n");
361            case TSDEV_CC_IPIR:
362                clearIPI(pkt->getLE<uint64_t>());
363                break;
364            case TSDEV_CC_ITIR:
365                clearITI(pkt->getLE<uint64_t>());
366                break;
367            case TSDEV_CC_IPIQ:
368                reqIPI(pkt->getLE<uint64_t>());
369                break;
370            default:
371              panic("default in cchip read reached, accessing 0x%x\n");
372        }  // swtich(regnum)
373    } // not BIG_TSUNAMI write
374    pkt->makeAtomicResponse();
375    return pioDelay;
376}
377
378void
379TsunamiCChip::clearIPI(uint64_t ipintr)
380{
381    int numcpus = sys->threadContexts.size();
382    assert(numcpus <= Tsunami::Max_CPUs);
383
384    if (ipintr) {
385        for (int cpunum=0; cpunum < numcpus; cpunum++) {
386            // Check each cpu bit
387            uint64_t cpumask = ULL(1) << cpunum;
388            if (ipintr & cpumask) {
389                // Check if there is a pending ipi
390                if (ipint & cpumask) {
391                    ipint &= ~cpumask;
392                    tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
393                    DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
394                }
395                else
396                    warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
397            }
398        }
399    }
400    else
401        panic("Big IPI Clear, but not processors indicated\n");
402}
403
404void
405TsunamiCChip::clearITI(uint64_t itintr)
406{
407    int numcpus = sys->threadContexts.size();
408    assert(numcpus <= Tsunami::Max_CPUs);
409
410    if (itintr) {
411        for (int i=0; i < numcpus; i++) {
412            uint64_t cpumask = ULL(1) << i;
413            if (itintr & cpumask & itint) {
414                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
415                itint &= ~cpumask;
416                DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
417            }
418        }
419    }
420    else
421        panic("Big ITI Clear, but not processors indicated\n");
422}
423
424void
425TsunamiCChip::reqIPI(uint64_t ipreq)
426{
427    int numcpus = sys->threadContexts.size();
428    assert(numcpus <= Tsunami::Max_CPUs);
429
430    if (ipreq) {
431        for (int cpunum=0; cpunum < numcpus; cpunum++) {
432            // Check each cpu bit
433            uint64_t cpumask = ULL(1) << cpunum;
434            if (ipreq & cpumask) {
435                // Check if there is already an ipi (bits 8:11)
436                if (!(ipint & cpumask)) {
437                    ipint  |= cpumask;
438                    tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
439                    DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
440                }
441                else
442                    warn("post IPI for CPU=%d, but IPI already\n", cpunum);
443            }
444        }
445    }
446    else
447        panic("Big IPI Request, but not processors indicated\n");
448}
449
450
451void
452TsunamiCChip::postRTC()
453{
454    int size = sys->threadContexts.size();
455    assert(size <= Tsunami::Max_CPUs);
456
457    for (int i = 0; i < size; i++) {
458        uint64_t cpumask = ULL(1) << i;
459       if (!(cpumask & itint)) {
460           itint |= cpumask;
461           tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
462           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
463       }
464    }
465
466}
467
468void
469TsunamiCChip::postDRIR(uint32_t interrupt)
470{
471    uint64_t bitvector = ULL(1) << interrupt;
472    uint64_t size = sys->threadContexts.size();
473    assert(size <= Tsunami::Max_CPUs);
474    drir |= bitvector;
475
476    for (int i=0; i < size; i++) {
477        dir[i] = dim[i] & drir;
478       if (dim[i] & bitvector) {
479              tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
480              DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
481                        "interrupt %d\n",i, interrupt);
482       }
483    }
484}
485
486void
487TsunamiCChip::clearDRIR(uint32_t interrupt)
488{
489    uint64_t bitvector = ULL(1) << interrupt;
490    uint64_t size = sys->threadContexts.size();
491    assert(size <= Tsunami::Max_CPUs);
492
493    if (drir & bitvector)
494    {
495        drir &= ~bitvector;
496        for (int i=0; i < size; i++) {
497           if (dir[i] & bitvector) {
498               tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
499               DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
500                    "interrupt %d\n",i, interrupt);
501
502           }
503           dir[i] = dim[i] & drir;
504        }
505    }
506    else
507        DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
508}
509
510
511void
512TsunamiCChip::serialize(CheckpointOut &cp) const
513{
514    SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
515    SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
516    SERIALIZE_SCALAR(ipint);
517    SERIALIZE_SCALAR(itint);
518    SERIALIZE_SCALAR(drir);
519}
520
521void
522TsunamiCChip::unserialize(CheckpointIn &cp)
523{
524    UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
525    UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
526    UNSERIALIZE_SCALAR(ipint);
527    UNSERIALIZE_SCALAR(itint);
528    UNSERIALIZE_SCALAR(drir);
529}
530
531TsunamiCChip *
532TsunamiCChipParams::create()
533{
534    return new TsunamiCChip(this);
535}
536