1803SN/A/* 21363SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 302665SN/A * Miguel Serrano 31803SN/A */ 32768SN/A 331730SN/A/** @file 34773SN/A * Tsunami I/O including PIC, PIT, RTC, DMA 35768SN/A */ 36768SN/A 3711793Sbrandon.potter@amd.com#include "dev/alpha/tsunami_io.hh" 3811793Sbrandon.potter@amd.com 39773SN/A#include <sys/time.h> 40773SN/A 41768SN/A#include <deque> 42768SN/A#include <string> 43768SN/A#include <vector> 44768SN/A 454762Snate@binkert.org#include "base/time.hh" 46768SN/A#include "base/trace.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488232Snate@binkert.org#include "debug/Tsunami.hh" 498229Snate@binkert.org#include "dev/alpha/tsunami.hh" 503540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 513540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 528229Snate@binkert.org#include "dev/rtcreg.h" 533348SN/A#include "mem/packet.hh" 543348SN/A#include "mem/packet_access.hh" 552542SN/A#include "mem/port.hh" 562542SN/A#include "sim/system.hh" 57768SN/A 588737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 598737Skoansin.tan@gmail.com// we open up the entire namespace std 608737Skoansin.tan@gmail.comusing std::string; 618737Skoansin.tan@gmail.comusing std::ostream; 628737Skoansin.tan@gmail.com 632107SN/A//Should this be AlphaISA? 642107SN/Ausing namespace TheISA; 65773SN/A 665606Snate@binkert.orgTsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) 675606Snate@binkert.org : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), 685606Snate@binkert.org tsunami(p->tsunami) 691817SN/A{ 70772SN/A} 71772SN/A 724762Snate@binkert.orgTsunamiIO::TsunamiIO(const Params *p) 739808Sstever@gmail.com : BasicPioDevice(p, 0x100), tsunami(p->tsunami), 745606Snate@binkert.org pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) 75768SN/A{ 76803SN/A // set the back pointer from tsunami to myself 77803SN/A tsunami->io = this; 78803SN/A 79771SN/A timerData = 0; 80777SN/A picr = 0; 81777SN/A picInterrupting = false; 82773SN/A} 83773SN/A 841634SN/ATick 851634SN/ATsunamiIO::frequency() const 861634SN/A{ 877064Snate@binkert.org return SimClock::Frequency / params()->frequency; 881634SN/A} 891634SN/A 902542SN/ATick 913349SN/ATsunamiIO::read(PacketPtr pkt) 92768SN/A{ 932641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 94768SN/A 952641SN/A Addr daddr = pkt->getAddr() - pioAddr; 96865SN/A 972641SN/A DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 982641SN/A pkt->getSize(), daddr); 99771SN/A 1002641SN/A if (pkt->getSize() == sizeof(uint8_t)) { 101803SN/A switch(daddr) { 1021817SN/A // PIC1 mask read 1031817SN/A case TSDEV_PIC1_MASK: 10413232Sgabeblack@google.com pkt->setLE(~mask1); 1052539SN/A break; 1061817SN/A case TSDEV_PIC2_MASK: 10713232Sgabeblack@google.com pkt->setLE(~mask2); 1082539SN/A break; 109865SN/A case TSDEV_PIC1_ISR: 110865SN/A // !!! If this is modified 64bit case needs to be too 111865SN/A // Pal code has to do a 64 bit physical read because there is 112865SN/A // no load physical byte instruction 11313232Sgabeblack@google.com pkt->setLE(picr); 1142539SN/A break; 115865SN/A case TSDEV_PIC2_ISR: 116865SN/A // PIC2 not implemnted... just return 0 11713232Sgabeblack@google.com pkt->setLE(0x00); 1182539SN/A break; 1191817SN/A case TSDEV_TMR0_DATA: 12013232Sgabeblack@google.com pkt->setLE(pitimer.readCounter(0)); 1212542SN/A break; 1221817SN/A case TSDEV_TMR1_DATA: 12313232Sgabeblack@google.com pkt->setLE(pitimer.readCounter(1)); 1242542SN/A break; 1251817SN/A case TSDEV_TMR2_DATA: 12613232Sgabeblack@google.com pkt->setLE(pitimer.readCounter(2)); 1272539SN/A break; 128803SN/A case TSDEV_RTC_DATA: 12913232Sgabeblack@google.com pkt->setLE(rtc.readData(rtcAddr)); 1302539SN/A break; 1311817SN/A case TSDEV_CTRL_PORTB: 1325635Sgblack@eecs.umich.edu if (pitimer.outputHigh(2)) 13313232Sgabeblack@google.com pkt->setLE(PORTB_SPKR_HIGH); 1341817SN/A else 13513232Sgabeblack@google.com pkt->setLE(0x00); 1362539SN/A break; 137803SN/A default: 1382641SN/A panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 139803SN/A } 1402641SN/A } else if (pkt->getSize() == sizeof(uint64_t)) { 1412539SN/A if (daddr == TSDEV_PIC1_ISR) 14213232Sgabeblack@google.com pkt->setLE<uint64_t>(picr); 1432539SN/A else 1442539SN/A panic("I/O Read - invalid addr - va %#x size %d\n", 1452641SN/A pkt->getAddr(), pkt->getSize()); 1462539SN/A } else { 1472641SN/A panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 148771SN/A } 1494870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1502539SN/A return pioDelay; 151768SN/A} 152768SN/A 1532539SN/ATick 1543349SN/ATsunamiIO::write(PacketPtr pkt) 155768SN/A{ 1562641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1572641SN/A Addr daddr = pkt->getAddr() - pioAddr; 158779SN/A 159779SN/A DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 16013232Sgabeblack@google.com pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, 16113232Sgabeblack@google.com (uint32_t)pkt->getLE<uint8_t>()); 162768SN/A 1632641SN/A assert(pkt->getSize() == sizeof(uint8_t)); 164769SN/A 1652539SN/A switch(daddr) { 1662539SN/A case TSDEV_PIC1_MASK: 16713232Sgabeblack@google.com mask1 = ~(pkt->getLE<uint8_t>()); 1682539SN/A if ((picr & mask1) && !picInterrupting) { 1692539SN/A picInterrupting = true; 1702539SN/A tsunami->cchip->postDRIR(55); 1712539SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 172803SN/A } 1732539SN/A if ((!(picr & mask1)) && picInterrupting) { 1742539SN/A picInterrupting = false; 1752539SN/A tsunami->cchip->clearDRIR(55); 1762539SN/A DPRINTF(Tsunami, "clearing pic interrupt\n"); 1772539SN/A } 1782539SN/A break; 1792539SN/A case TSDEV_PIC2_MASK: 18013232Sgabeblack@google.com mask2 = pkt->getLE<uint8_t>(); 1812539SN/A //PIC2 Not implemented to interrupt 1822539SN/A break; 1832539SN/A case TSDEV_PIC1_ACK: 1842539SN/A // clear the interrupt on the PIC 18513232Sgabeblack@google.com picr &= ~(1 << (pkt->getLE<uint8_t>() & 0xF)); 1862539SN/A if (!(picr & mask1)) 1872539SN/A tsunami->cchip->clearDRIR(55); 1882539SN/A break; 1892539SN/A case TSDEV_DMA1_MODE: 19013232Sgabeblack@google.com mode1 = pkt->getLE<uint8_t>(); 1912539SN/A break; 1922539SN/A case TSDEV_DMA2_MODE: 19313232Sgabeblack@google.com mode2 = pkt->getLE<uint8_t>(); 1942539SN/A break; 1952539SN/A case TSDEV_TMR0_DATA: 19613232Sgabeblack@google.com pitimer.writeCounter(0, pkt->getLE<uint8_t>()); 1972539SN/A break; 1982539SN/A case TSDEV_TMR1_DATA: 19913232Sgabeblack@google.com pitimer.writeCounter(1, pkt->getLE<uint8_t>()); 2002539SN/A break; 2012539SN/A case TSDEV_TMR2_DATA: 20213232Sgabeblack@google.com pitimer.writeCounter(2, pkt->getLE<uint8_t>()); 2032539SN/A break; 2042539SN/A case TSDEV_TMR_CTRL: 20513232Sgabeblack@google.com pitimer.writeControl(pkt->getLE<uint8_t>()); 2062539SN/A break; 2072539SN/A case TSDEV_RTC_ADDR: 20813232Sgabeblack@google.com rtcAddr = pkt->getLE<uint8_t>(); 2092539SN/A break; 2102539SN/A case TSDEV_RTC_DATA: 21113232Sgabeblack@google.com rtc.writeData(rtcAddr, pkt->getLE<uint8_t>()); 2122539SN/A break; 2132539SN/A case TSDEV_KBD: 2142539SN/A case TSDEV_DMA1_CMND: 2152539SN/A case TSDEV_DMA2_CMND: 2162539SN/A case TSDEV_DMA1_MMASK: 2172539SN/A case TSDEV_DMA2_MMASK: 2182539SN/A case TSDEV_PIC2_ACK: 2192539SN/A case TSDEV_DMA1_RESET: 2202539SN/A case TSDEV_DMA2_RESET: 2212539SN/A case TSDEV_DMA1_MASK: 2222539SN/A case TSDEV_DMA2_MASK: 2232539SN/A case TSDEV_CTRL_PORTB: 2242539SN/A break; 225803SN/A default: 22613232Sgabeblack@google.com panic("I/O Write - va%#x size %d data %#x\n", 22713232Sgabeblack@google.com pkt->getAddr(), pkt->getSize(), pkt->getLE<uint8_t>()); 228769SN/A } 229769SN/A 2304870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2312539SN/A return pioDelay; 232768SN/A} 233768SN/A 234768SN/Avoid 235777SN/ATsunamiIO::postPIC(uint8_t bitvector) 236777SN/A{ 237777SN/A //PIC2 Is not implemented, because nothing of interest there 238777SN/A picr |= bitvector; 239865SN/A if (picr & mask1) { 240817SN/A tsunami->cchip->postDRIR(55); 241777SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 242777SN/A } 243777SN/A} 244777SN/A 245777SN/Avoid 246777SN/ATsunamiIO::clearPIC(uint8_t bitvector) 247777SN/A{ 248777SN/A //PIC2 Is not implemented, because nothing of interest there 249777SN/A picr &= ~bitvector; 250777SN/A if (!(picr & mask1)) { 251817SN/A tsunami->cchip->clearDRIR(55); 252777SN/A DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 253777SN/A } 254777SN/A} 255777SN/A 256777SN/Avoid 25710905Sandreas.sandberg@arm.comTsunamiIO::serialize(CheckpointOut &cp) const 258768SN/A{ 2595392Sgblack@eecs.umich.edu SERIALIZE_SCALAR(rtcAddr); 260811SN/A SERIALIZE_SCALAR(timerData); 261899SN/A SERIALIZE_SCALAR(mask1); 262899SN/A SERIALIZE_SCALAR(mask2); 263899SN/A SERIALIZE_SCALAR(mode1); 264899SN/A SERIALIZE_SCALAR(mode2); 265811SN/A SERIALIZE_SCALAR(picr); 266811SN/A SERIALIZE_SCALAR(picInterrupting); 267811SN/A 268919SN/A // Serialize the timers 26910905Sandreas.sandberg@arm.com pitimer.serialize("pitimer", cp); 27010905Sandreas.sandberg@arm.com rtc.serialize("rtc", cp); 271768SN/A} 272768SN/A 273768SN/Avoid 27410905Sandreas.sandberg@arm.comTsunamiIO::unserialize(CheckpointIn &cp) 275768SN/A{ 2765392Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(rtcAddr); 277811SN/A UNSERIALIZE_SCALAR(timerData); 278899SN/A UNSERIALIZE_SCALAR(mask1); 279899SN/A UNSERIALIZE_SCALAR(mask2); 280899SN/A UNSERIALIZE_SCALAR(mode1); 281899SN/A UNSERIALIZE_SCALAR(mode2); 282811SN/A UNSERIALIZE_SCALAR(picr); 283811SN/A UNSERIALIZE_SCALAR(picInterrupting); 284919SN/A 285919SN/A // Unserialize the timers 28610905Sandreas.sandberg@arm.com pitimer.unserialize("pitimer", cp); 28710905Sandreas.sandberg@arm.com rtc.unserialize("rtc", cp); 288768SN/A} 289768SN/A 29010631Scdirik@micron.comvoid 29110631Scdirik@micron.comTsunamiIO::startup() 29210631Scdirik@micron.com{ 29310631Scdirik@micron.com rtc.startup(); 29410642Scdirik@micron.com pitimer.startup(); 29510631Scdirik@micron.com} 29610631Scdirik@micron.com 2974762Snate@binkert.orgTsunamiIO * 2984762Snate@binkert.orgTsunamiIOParams::create() 299768SN/A{ 3004762Snate@binkert.org return new TsunamiIO(this); 301768SN/A} 302