Searched hist:12110 (Results 1 - 23 of 23) sorted by relevance
| /gem5/src/cpu/ | ||
| H A D | StaticInstFlags.py | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | static_inst.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base_dyn_inst.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/sim/ | ||
| H A D | fd_array.hh | 13029:75abda747dc3 Wed Apr 18 14:42:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> syscall_emul: style changes and FDArray refactor Some members were defined as public when they should have been privately declared so these were moved to the appropriate spot. The operator[] had inline specified for for an in-class definition which is redundant since inline definitions are always implicitly inline. Private members had the leading underscore applied to them to denote that they're private (consistent with style guide). Changed static const defined class variable into a constexpr with brace-list initialization. Change-Id: If3054416b57827d1542e9ebab428d67d0e767723 Reviewed-on: https://gem5-review.googlesource.com/12110 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | fd_array.cc | 13029:75abda747dc3 Wed Apr 18 14:42:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> syscall_emul: style changes and FDArray refactor Some members were defined as public when they should have been privately declared so these were moved to the appropriate spot. The operator[] had inline specified for for an in-class definition which is redundant since inline definitions are always implicitly inline. Private members had the leading underscore applied to them to denote that they're private (consistent with style guide). Changed static const defined class variable into a constexpr with brace-list initialization. Change-Id: If3054416b57827d1542e9ebab428d67d0e767723 Reviewed-on: https://gem5-review.googlesource.com/12110 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | fp64.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | neon64.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/alpha/ | ||
| H A D | faults.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | faults.cc | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/alpha/isa/ | ||
| H A D | fp.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/templates/ | ||
| H A D | pred.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | mem.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/sparc/isa/ | ||
| H A D | base.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/sparc/ | ||
| H A D | faults.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | faults.cc | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | inst_queue.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | commit.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | inst_queue_impl.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | commit_impl.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/simple/ | ||
| H A D | exec_context.hh | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base.cc | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/ | ||
| H A D | operands.isa | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/ | ||
| H A D | isa_parser.py | 12110:c24ee249b8ba Wed Apr 05 14:24:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2706 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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