Searched hist:12 (Results 76 - 100 of 2449) sorted by relevance
/gem5/src/base/ | ||
H A D | atomicio.hh | 11235:4162427127e9 Thu Dec 03 19:12:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Add support for generating back traces on errors Add functionality to generate a back trace if gem5 crashes (SIGABRT or SIGSEGV). The current implementation uses glibc's stack traversal support if available and stubs out the call to print_backtrace() otherwise. 5548:19d45fa7315c Fri Sep 19 12:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> atomicio: provide atomic read and write functions. These functions keep trying to read and write until all data has been transferred, or an error occurrs. In the case where an end of file hasn't been reached, but all of the bytes have not been read/written, try again. On EINTR, try again. |
/gem5/util/cpt_upgraders/ | ||
H A D | etherswitch.py | 11776:ed89cb178ecd Mon Dec 19 01:12:00 EST 2016 Curtis Dunham <Curtis.Dunham@arm.com> dist, dev: fix etherswitch upgrade script The aforementioned upgrader in [1] assumes every option in [system] has a delimiting '.', and also seems to do its rewriting work a bit too unconditionally. Most checkpoints in the wild don't have this device, in which case this script should be a safe no-op. [1] 2aa4d7b dist, dev: Fixed the packet ordering in etherswitch Change-Id: Icfd0350985109df1628eb9ab864cda42c54060a8 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> 11533:2aa4d7bd47ec Wed Jun 08 10:12:00 EDT 2016 Mohammad Alian <m.alian1369@gmail.com> dist, dev: Fixed the packet ordering in etherswitch This patch fixes the order that packets gets pushed into the output fifo of etherswitch. If two packets arrive at the same tick to the etherswitch, we sort and push them based on their source port id. In dist-gem5 simulations, if there is no ordering inforced while two packets arrive at the same tick, it can lead to non-deterministic simulations Committed by Jason Lowe-Power <power.jg@gmail.com> |
/gem5/src/cpu/testers/traffic_gen/ | ||
H A D | dram_rot_gen.cc | 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | linear_gen.cc | 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | random_gen.cc | 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | idle_gen.cc | 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> 12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files. Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/mem/slicc/ast/ | ||
H A D | ExprAST.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/src/arch/x86/isa/insts/general_purpose/ | ||
H A D | __init__.py | 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode. |
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/ | ||
H A D | general_io.py | 5968:6f9f1438360a Fri Feb 27 12:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make instructions that use intseg preserve all 8 bytes of their addresses. 5418:501cb81c89df Thu Jun 12 00:47:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Bypass unaligned access support for register addressed MSRs. 5322:db50c4044662 Sat Jan 12 06:37:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the general IO instructions dataSize. 5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0. |
H A D | string_io.py | 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them. 5420:dc0041a51920 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make string instructions work when rcx=0. 5418:501cb81c89df Thu Jun 12 00:47:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Bypass unaligned access support for register addressed MSRs. 5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0. |
/gem5/src/mem/ | ||
H A D | drampower.hh | 10431:d9415c7f61a9 Tue Jul 29 12:29:00 EDT 2014 Omar Naji <Omar.Naji@arm.com> mem: Add DRAMPower wrapping class This patch adds a class to wrap DRAMPower Library in gem5. This class initiates an object of class MemorySpecification of the DRAMPower Library, passes the parameters from DRAMCtrl.py to this object and creates an object of drampower library using the memory specification. |
/gem5/src/dev/net/ | ||
H A D | etherdevice.cc | 11522:348411ec525a Mon Jun 06 12:16:00 EDT 2016 Stephan Diestelhorst <stephan.diestelhorst@arm.com> sim: Call regStats of base-class as well We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there. Patch originally provided by Akash Bagdia at ARM Ltd. |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/ | ||
H A D | simerr | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/ | ||
H A D | simerr | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/ | ||
H A D | simerr | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/ | ||
H A D | simerr | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/ | ||
H A D | config.ini | 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP |
H A D | simerr | 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP |
/gem5/src/arch/power/insts/ | ||
H A D | mem.cc | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/sim/ | ||
H A D | microcode_rom.hh | 5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA. |
/gem5/ext/testlib/ | ||
H A D | __init__.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | config.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | helper.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | log.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | query.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
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